IS43R16800A-5TL-TR ISSI, Integrated Silicon Solution Inc, IS43R16800A-5TL-TR Datasheet - Page 11

• Manufacturer Part Number: IS43R16800A-5TL-TR
• Description: IC DDR SDRAM 128MBIT 66TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS43R16800A-5TL-TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOPII
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS43R16800A
MODE REGISTER DEFINITION
The mode register allows configuration of the operat-
ing mode of the DDR SDRAM. This register is loaded
as a step in the normal initialization of the device.
The Load Mode Register command samples the
values on inputs A0-A11, BA0 (Low) and BA1 (Low)
and stores them as register values M0-M13. The
values in the register determine the burst length,
burst type, CAS latency timing, and DLL Reset/Clear.
It should be noted that some bit values are reserved
and should not be loaded into the register. The data
in the mode register is retained until it is re-loaded or
the DDR SDRAM loses its power (except for bit M8,
which is cleared automatically). The register can be
MODE REGISTER DEFINITION
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
07/11/05
BA1 BA0 A11 A10
Operating Mode
M13 M12
0
—
—
0
M11
—
0
A9
M10
0
—
Operating Mode
A8
M8 M7
— —
0
1
M9
0
—
0
0
A7
Mode
Standard operation
All Other States Reserved
Defined
Defined
M6-M0
—
Latency Mode
A6
M6 M5 M4
0
0
0
0
1
1
1
1
Mode
Standard Operation
Standard Operation w/DLL Reset
All Other States Reserved
0
0
1
1
0
0
1
1
A5
0
1
0
1
0
1
0
1
A4
Burst Type
CAS Latency
M3
loaded only if all banks are idle. After the Load
Mode Register command, a minimum time of tMRD
must pass before the subsequent command is
issued.
CAS LATENCY
After a Read command is issued to the device, a
latency of several clock cycles is necessary prior to
the validity of data on the data bus. Also known as
CAS Latency (CL), the value must be configured as 3,
via the bits M4-M6 loaded into the register. If CL values
are not defined, the device may not function properly.
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
A3
3
Interleaved
Sequential
A2
Burst Length
Type
M2
0
0
0
0
1
1
1
1
A1
M1
0
0
1
1
0
0
1
1
M0
0
1
0
1
0
1
0
1
A0
Reserved
Reserved
Reserved
Reserved
Reserved
Address Bus (Ax)
Mode Register (Mx)
M3=0
2
4
8
Reserved
Reserved
Reserved
Reserved
Reserved
M3=1
2
4
8
ISSI
11
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