IS43R16800A-5TL-TR ISSI, Integrated Silicon Solution Inc, IS43R16800A-5TL-TR Datasheet - Page 31

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IS43R16800A-5TL-TR

Manufacturer Part Number
IS43R16800A-5TL-TR
Description
IC DDR SDRAM 128MBIT 66TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet

Specifications of IS43R16800A-5TL-TR

Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
128M (8Mx16)
Speed
200MHz
Interface
Parallel
Voltage - Supply
2.5 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOPII
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
IS43R16800A
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
07/11/05
A Read command to the consecutive Write command interval with the BST command
1. Same
2. Same
3. Different
Command
Destination row of the consecutive write
command
Bank
address
DQS
/CK
DM
DQ
CK
Row address State
Same
Different
Any
READ
High-Z
t0
BST
ACTIVE
ACTIVE
IDLE
t1
tBSTW ( tBSTZ)
READ to WRITE Command Interval
t2
tBSTZ (= CL)
Operation
Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the
consecutive write command can be issued.
Precharge the bank to interrupt the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive write command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the
consecutive write command can be issued.
Precharge the bank independently of the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive write command can be issued.
NOP
OUTPUT
t3
out0 out1
WRIT
t4
in0
t5
in1
in2
INPUT
t6
NOP
in3
t7
BL = 4
CL = 3
t8
ISSI
31
®

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