IS43R16800A-6T ISSI [Integrated Silicon Solution, Inc], IS43R16800A-6T Datasheet

IS43R16800A-6T

Manufacturer Part Number

IS43R16800A-6T

Description

8Meg x 16 128-MBIT DDR SDRAM

Manufacturer

ISSI [Integrated Silicon Solution, Inc]

Datasheet

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IS43R16800A-6

FEATURES

•

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. 00A

04/04/06

8Meg x 16

128-MBIT DDR SDRAM

Clock Frequency: 166, 133 MHz

Power supply (V

SSTL 2 interface

Four internal banks to hide row Pre-charge

and Active operations

Commands and addresses register on positive

clock edges (CK)

Bi-directional Data Strobe signal for data cap-

ture

Differential clock inputs (CK and CK) for

two data accesses per clock cycle

Data Mask feature for Writes supported

DLL aligns data I/O and Data Strobe transitions

with clock inputs

Half-strength and Matched drive strength

options

Programmable burst length for Read and Write

operations

Programmable CAS Latency (2, 2.5 clocks)

Programmable burst sequence: sequential or

interleaved

Burst concatenation and truncation supported

for maximum data throughput

Auto Pre-charge option for each Read or Write

burst

4096 refresh cycles every 64ms

Auto Refresh and Self Refresh Modes

Pre-charge Power Down and Active Power

Down Modes

Lead-free Availability

and V

DDQ

): 2.5V

DEVICE OVERVIEW

ISSI’s 128-Mbit DDR SDRAM achieves high-speed data

transfer using pipeline architecture and two data word

accesses per clock cycle. The 134,217,728-bit memory

array is internally organized as four banks of 32M-bit to

allow concurrent operations. The pipeline allows Read

and Write burst accesses to be virtually continuous, with

the option to concatenate or truncate the bursts. The

programmable features of burst length, burst sequence

and CAS latency enable further advantages. The device

is available in 16-bit data word size. Input data is regis-

tered on the I/O pins on both edges of Data Strobe

signal(s), while output data is referenced to both edges of

Data Strobe and both edges of CK. Commands are

registered on the positive edges of CK. Auto Refresh,

Active Power Down, and Pre-charge Power Down modes

are enabled by using clock enable (CKE) and other

inputs in an industry-standard sequence. All input and

output voltage levels are compatible with SSTL 2.

IS43R16800A-6

1M x16x8 Banks

66-pin TSOP-II

KEY TIMING PARAMETERS

Parameter

Clock Cycle Time

Clock Frequency

DDQ

: 2.5V

CAS Latency = 3

CAS Latency = 2.5

CAS Latency = 2

CAS Latency = 3

CAS Latency = 2.5

CAS Latency = 2

: 2.5V

PRELIMINARY INFORMATION

APRIL 2006

DDR333

166

133

7.5

—

-6

Unit

MHz

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