IS43R16800A-5TL-TR ISSI, Integrated Silicon Solution Inc, IS43R16800A-5TL-TR Datasheet

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... CLK. Auto Refresh, Active Power Down, and Pre-charge Power Down modes are enabled by using clock enable (CKE) and other inputs in an industry-standard sequence. All input and output voltage levels are compatible with SSTL 2. IS43R16800A 1M x16x8 Banks ...

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... IS43R16800A FUNCTIONAL BLOCK DIAGRAM ( CLK COMMAND CLK DECODER CKE & CS CLOCK RAS GENERATOR CAS WE MODE REGISTER A11 14 A10 ROW BA0 ADDRESS BA1 LATCH 14 COLUMN ADDRESS LATCH 9 BURST COUNTER COLUMN ADDRESS BUFFER 2 16) X REFRESH CONTROLLER SELF REFRESH CONTROLLER REFRESH COUNTER ROW ADDRESS ...

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... IS43R16800A PIN CONFIGURATIONS 66 pin TSOP - Type II for x16 V DD DQ0 V DD DQ1 DQ2 V SS DQ3 DQ4 V DD DQ5 DQ6 V SS DQ7 NC V DDQ LDQS NC VDD NC LDM WE CAS RAS CS NC BA0 BA1 A10 VDD PIN DESCRIPTIONS A0-A11 Row Address Input A0-A8 Column Address Input ...

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... IS43R16800A PIN FUNCTIONS Symbol Type A0-A11 Input Pin BA0, BA1 Input Pin CAS Input Pin CKE Input Pin CLK, CLK Input Pin CS Input Pin LDM, UDM Input Pin LDQS, UDQS Input/Output Pin DQ0-DQ15 Input/Output Pin NC — RAS Input Pin WE Input Pin ...

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... IS43R16800A ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage DD MAX V Maximum Supply Voltage for Output Buffer DDQ MAX Input Voltage, Reference Voltage IN REF P Allowable Power Dissipation D MAX I Output Shorted Current CS T Operating Temperature OPR T Storage Temperature STG Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...

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... IS43R16800A CAPACITANCE CHARACTERISTICS Symbol Parameter Input Capacitance: CLK and CLK C IN1 C Input Capacitance: All other input pins IN2 C 3 Data Mask Input/Output Capacitance: LDM/UDM IN C Data Input/Output Capacitance: DQs and LDQS/UDQS OUT DC ELECTRICAL CHARACTERISTICS Symbol Parameter I Operating Current Operating Current 1 DD ...

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... IS43R16800A AC ELECTRICAL CHARACTERISTICS (V Symbol Parameter t Clock Cycle Time CK t Clock High Level Width CH t Clock Low Level Width CL t Clock Half Period HP Output Access Time from CLK, CLK t AC DQS-Out Access Time from CLK, CLK t DQSCK t DQS-DQ Skew DQSQ t Output DQS Valid Window ...

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... IS43R16800A Notes: 1. All AC parameters measuremed with the following test conditions. 2. This parameter defines the signal transition delay from the crossing point of CK and CK. The signal transition is defined to occur when the signal level crosses VTT. 3. The timing reference level is VTT. 4. Output valid window is defined to be the period between two successive transition of data out or DQS (read) signals. The signal transition is defined to occur when the signal level crosses VTT ...

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... IS43R16800A AC TEST CONDITIONS Output Load TEST CONDITIONS Parameter Input High Voltage Input Low Voltage Input Signal Slew Rate Input Timing Reference Level Termination Voltage Input Differential Voltage (CLK and CLK) Input Differential Crossing Voltage OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER t Write to Pre-charge command delay (same bank) ...

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... IS43R16800A FUNCTIONAL DESCRIPTION The 128Mbit DDR SDRAM is a high-speed CMOS device with four banks that operate at 2.6V. Each 32Mbit bank is organized as 4,096 rows of 512 columns for the x16 option. Pre-fetch architecture allows Read and Write accesses to be double-data rate and burst oriented ...

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... IS43R16800A MODE REGISTER DEFINITION The mode register allows configuration of the operat- ing mode of the DDR SDRAM. This register is loaded as a step in the normal initialization of the device. The Load Mode Register command samples the values on inputs A0-A11, BA0 (Low) and BA1 (Low) and stores them as register values M0-M13 ...

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... IS43R16800A BURST LENGTH The highest access throughput of this device can be achieved by using a burst of either Read or Write accesses. The number of accesses in each burst would be pre-configured shown in Mode Register Definition (bits M0-M2). When a Read or Write command is given to the device, the address bits A0-A8 (x16) select the block of columns and the starting column for the subsequent burst ...

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... IS43R16800A EXTENDED MODE REGISTER DEFINITION The Extended Mode Register is a second register to enable additional functions of the DDR SDRAM. This register is loaded as a step in the normal initialization of the device. The Load Extended Mode Register command samples the values on inputs A0-A11, BA0 (High) and BA1 (Low) and stores them as register values E0-E13 ...

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... IS43R16800A COMMANDS All commands described in this section should be issued only when the initialization sequence is obeyed. Deselect (DESL) This feature blocks unwanted commands from being executed. Chip select (CS) must be taken High to cause Deselect. Operations that are underway are not affected. No Operation (NOP) NOP is a command that prevents new commands from being executed ...

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... IS43R16800A Auto Refresh (REF) The DDR SDRAM is issued the Auto Refresh com- mand during normal operation to maintain data in the memory array. All the banks must be idle for the command to be executed. The device has 4096 refresh cycles every 64ms. Self Refresh (SELF) To issue the Self Refresh command, CKE must be Low ...

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... IS43R16800A Write Operation A Write command starts a burst from an activated row. The Write command is depicted in the figure. As CLK goes High, CS, WE, and CAS are Low, while CKE and RAS are High. The values on the inputs BA0 and BA1 specify the bank to access, and the address inputs specify the starting column in the open row ...

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... IS43R16800A COMMAND TRUTH TABLE DDR SDRAM recognize the following commands specified by the CS, RAS, CAS, WE and address pins. All other combinations than those in the table below are illegal. Command Ignore command No operation Burst stop in read command Column address and read command Read with auto-precharge ...

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... IS43R16800A Function Truth Table The following tables show the operations that are performed when each command is issued in each state of the DDR SDRAM. Current state /CS /RAS /CAS /WE 1 Precharging Idle Refresh H 3 (auto-refresh Activating Active Address Command DESL H H NOP H L BST ...

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... IS43R16800A Current state /CS /RAS /CAS /WE 6 Read Read with auto-pre charge Write Write recovering Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/05 Address Command DESL H NOP L BST H BA, CA, A10 READ/READA L BA, CA, A10 WRIT/WRITA H BA, RA ACT L BA, A10 PRE, PALL DESL ...

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... IS43R16800A Current state /CS /RAS /CAS /WE Write with auto pre-charge Remark: H: VIH. L: VIL. : VIH or VIL Notes: 1. The DDR SDRAM is in "Precharging" state for tRP after precharge command is issued. 2. The DDR SDRAM reaches "IDLE" state tRP after precharge command is issued. 3. The DDR SDRAM is in "Refresh" state for tRFC after auto-refresh command is issued. ...

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... IS43R16800A Command Truth Table for CKE Current State CKE n – /CS Self refresh Self refresh recovery Power down All banks idle Row active H L Remark: H: VIH. L: VIL. : VIH or VIL Note: Self refresh can be entered only from the all banks idle state. Power down can be entered only from all banks idle or row active state. Integrated Silicon Solution, Inc. — ...

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... IS43R16800A Simplified State Diagram ACTIVE POWER Write POWER APPLIED Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state. 22 REFRESH SR ENTRY SR EXIT MRS REFRESH MRS IDLE REFRESH ...

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... IS43R16800A Read/Write Operations Bank active A read or a write operation begins with the bank active command [ACT]. The bank active command determines a bank address and a row address. For the bank and the row, a read or a write command can be issued tRCD after the ACT is issued. ...

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... IS43R16800A t0 CK /CK READ Command DQS Write operation The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued. The burst length (BL) determines the length of a sequential data input by the write command that can be set The latency from write command to data input is fixed to 1. The starting address of the burst read is defined by the column address, the bank select address which are loaded via the A0 to A11, BA0 to BA1 pins in the cycle when the write command is issued ...

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... IS43R16800A Burst Stop Burst stop command during burst read The burst stop (BST) command is used to stop data output during a burst read. The BST command stops the burst read and sets the output buffer to High-Z. tBSTZ (= CL) cycles after a BST command issued, the DQ pins become High-Z ...

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... IS43R16800A Auto Precharge Read with auto-precharge The precharge is automatically performed after completing a read operation. The precharge starts tRPD (BL/2) cycle after READA command input. tRAP specification for READA allows a read command with auto precharge to be issued to a bank that has been activated (opened) but has not yet satisfied the tRAS (min) specification. A column command to the other active bank can be issued the next cycle after the last data output ...

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... IS43R16800A Command Intervals A Read command to the consecutive Read command Interval Destination row of the consecutive read command Bank Row address State address 1. Same Same ACTIVE 2. Same Different — 3. Different Any ACTIVE IDLE t0 CK /CK Command ACT NOP Row Column A Address BA DQ DQS Bank0 ...

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... IS43R16800A /CK Command ACT NOP Row0 Address BA DQ DQS Bank0 Active READ READ ACT NOP Row1 Column A Column B Column = A Read Bank3 Bank0 Bank3 Active Read Read READ to READ Command Interval (different bank) Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI t10 NOP out ...

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... IS43R16800A A Write command to the consecutive Write command Interval Destination row of the consecutive write command Bank Row address State address 1. Same Same ACTIVE 2. Same Different — 3. Different Any ACTIVE IDLE t0 CK /CK Command ACT NOP Row Address BA DQ DQS Bank0 Active WRITE to WRITE Command Interval (same ROW address in the same bank) Integrated Silicon Solution, Inc. — ...

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... IS43R16800A /CK Command ACT NOP Row0 Address BA DQ DQS Bank0 Active tn+1 ACT NOP WRIT WRIT Row1 Column A Column B inA0 inA1 inB0 inB1 inB2 inB3 Bank0 Write Bank3 Active WRITE to WRITE Command Interval (different bank) Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI ...

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... IS43R16800A A Read command to the consecutive Write command interval with the BST command Destination row of the consecutive write command Bank Row address State address 1. Same Same ACTIVE 2. Same Different — 3. Different Any ACTIVE IDLE /CK Command READ BST DM DQ High-Z DQS Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev ...

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... IS43R16800A A Write command to the consecutive Read command interval: To complete the burst operation Destination row of the consecutive read command Bank Row address State address 1. Same Same ACTIVE 2. Same Different — 3. Different Any ACTIVE IDLE /CK Command WRIT DM DQ in0 DQS Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR. ...

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... IS43R16800A A Write command to the consecutive Read command interval: To interrupt the write operation Destination row of the consecutive read command Bank Row address State address 1. Same Same ACTIVE 2. Same Different — 3. Different Any ACTIVE IDLE Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write operation in this case ...

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... IS43R16800A t0 CK /CK Command WRIT NOP 2 cycle DM DQ in0 DQS /CK Command WRIT DM DQ in0 DQS Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR READ CL=3 in1 in2 in3 Data masked [WRITE to READ delay = 2 clock cycle] ...

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... IS43R16800A A Read command to the consecutive Precharge command interval (same bank): To output all data To complete a burst read operation and get a burst length of data, the consecutive precharge command must be issued tRPD (= BL/ 2 cycles) after the read command is issued /CK Command NOP READ DQ DQS tRPD = BL/2 ...

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... IS43R16800A A Write command to the consecutive Precharge command interval (same bank) The minimum interval tWPD is necessary between the write command and the precharge command /CK Command WRIT DM DQS DQ WRITE to PRECHARGE Command Interval (same bank) ( Precharge Termination in Write Cycles During a burst write cycle without auto precharge, the burst write operation is terminated by a precharge command of the same bank ...

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... IS43R16800A Bank active command interval Destination row of the consecutive ACT command Bank Row address address State 1. Same Any ACTIVE 2. Different Any ACTIVE IDLE CK /CK Command ACTV ACT Address ROW Bank0 Active tRRD Mode register set to Bank-active command interval The interval between setting the mode register and executing a bank-active command must be no less than tMRD. ...

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... IS43R16800A DM Control DM can mask input data products, UDM and LDM can mask the upper and lower byte of input data, respectively. By setting DM to Low, data can be written. When DM is set to High, the corresponding data is not written, and the previous data is held. The latency between DM input and enabling/disabling mask function is 0. ...

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... IS43R16800A Timing Waveforms Command and Addresses Input Timing Definition CK /CK Command (/RAS, /CAS, /WE, /CS) Address Read Timing Definition tCK /CK CK tCH tRPRE DQS DQ (Dout) Write Timing Definition tCK /CK CK tDQSS DQS tWPRES tWPRE DQ (Din) DM Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A ...

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... IS43R16800A Read Cycle tCK tCH tCL CK /CK VIH CKE tRCD tIS tIH /CS tIS tIH /RAS tIS tIH /CAS tIS tIH /WE tIS tIH BA tIS tIH A10 tIS tIH Address DM High-Z DQS High-Z DQ (output) Bank 0 Bank 0 Active Active 40 tRC tRAS tIS tIH tIS tIH ...

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... IS43R16800A Write Cycle tCK tCH tCL CK /CK VIH CKE tRCD tIS tIH /CS tIS tIH /RAS tIS tIH /CAS tIS tIH /WE tIS tIH BA tIS tIH A10 tIS tIH Address DQS (input (input) Bank 0 Bank 0 Active Active Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev ...

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... IS43R16800A Mode Register Set Cycle 0 1 /CK CK VIH CKE /CS /RAS /CAS /WE BA Address valid DM High-Z DQS High-Z DQ (output) tRP Precharge If needed Read/Write Cycle /CK CK VIH CKE /CS /RAS /CAS /WE BA Address R:a DM DQS DQ (output) High-Z DQ (input) Bank 0 Active code code tMRD Bank 3 ...

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... IS43R16800A Auto Refresh Cycle /CK CK VIH CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ (output) DQ (input) tRP Precharge If needed Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/05 High-Z tRFC Auto Bank 0 Refresh Active ISSI Bank 0 Read VIH or VIL ® 43 ...

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... IS43R16800A Self Refresh Cycle /CK CK CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ (output) DQ (input) Precharge If needed 44 tIS tIH CKE = low High-Z tRP Self Self refresh refresh exit entry Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI tSNR tSRD Bank 0 Bank 0 Active Read ...

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... IS43R16800A ORDERING INFORMATION Commercial Range: 0°C to +70°C Frequency Speed (ns) 400 MHz 5 400 MHz 5 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/05 Order Part No. Package IS43R16800A-5T 66-pin TSOP-II IS43R16800A-5TL 66-pin TSOP-II, Lead-free ISSI ® 45 ...

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PACKAGING INFORMATION Plastic TSOP 66-pin Package Code: T (Type II Plastic TSOP (T - Type II) Millimeters Symbol Min Max Ref. Std. No. Leads ( — 1.20 A1 0.05 0.15 A2 — — ...