IS43R16800A-5TL-TR ISSI, Integrated Silicon Solution Inc, IS43R16800A-5TL-TR Datasheet - Page 33

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IS43R16800A-5TL-TR

Manufacturer Part Number
IS43R16800A-5TL-TR
Description
IC DDR SDRAM 128MBIT 66TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet

Specifications of IS43R16800A-5TL-TR

Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
128M (8Mx16)
Speed
200MHz
Interface
Parallel
Voltage - Supply
2.5 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOPII
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
IS43R16800A
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
07/11/05
A Write command to the consecutive Read command interval: To interrupt the write operation
1. Same
2. Same
3. Different
Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write
WRITE to READ Command Interval (Same bank, same ROW address)
Command
Destination row of the consecutive read
command
Bank
address
DQS
/CK
DM
DQ
CK
operation in this case.
Row address State
Same
Different
Any
WRIT
t0
1 cycle
READ
ACTIVE
ACTIVE
IDLE
in0
Data masked
t1
in1
[WRITE to READ delay = 1 clock cycle]
in2
t2
Operation
—*
—*
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
1
1
CL=3
t3
t4
out0 out1 out2 out3
t5
NOP
t6
t7
High-Z
High-Z
t8
BL = 4
CL = 3
ISSI
33
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