IS43R16800A-5TL-TR ISSI, Integrated Silicon Solution Inc, IS43R16800A-5TL-TR Datasheet - Page 6

• Manufacturer Part Number: IS43R16800A-5TL-TR
• Description: IC DDR SDRAM 128MBIT 66TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS43R16800A-5TL-TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOPII
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS43R16800A
DC ELECTRICAL CHARACTERISTICS
Notes:
1. Operating outside the “Absolute Maximum Ratings” may lead to temporary or permanent device failure.
2. Power up sequence describe in “Initialization” section.
3. All voltages are referenced to V
4. I
5. I
6
CAPACITANCE CHARACTERISTICS
Symbol Parameter
I
I
I
I
I
I
I
I
I
I
I
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
Symbol
C
C
C
C
0
1
2
2
3
3
4
4
5
6
7
OUT
IN1
IN2
IN
values tested with t
F
N
R
W
tested without DQ pins connected.
Q
P
3
Operating Current
Operating Current
Precharge Power-Down
Standby Current
Idle Standby Current
Active Power-Down
Standby Current
Active Standby Current
Operating Current
Burst Read
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current
Burst Write
Parameter
Input Capacitance: CLK and CLK
Input Capacitance: All other input pins
Data Mask Input/Output Capacitance: LDM/UDM
Data Input/Output Capacitance: DQs and LDQS/UDQS
CK
= t
CK
(min).
SS
.
Test Condition
One bank operation; Active-Precharge; DQ, DM and DQS
inputs change once per clock cycle; Address and Control
inputs change once per two clock cycles; tRC = tRC (min)
One bank operation; Active-Read-Precharge; BL = 4; CL = 4;
Address and Control inputs change once per clock cycle;
tRCDRD = 4 x tCK; tRC = tRC (min); IOUT = 0mA;
All banks Idle; tCK = tCK (min); CKE = Low
All banks idle; Address and control inputs change once per
clock cycle; CKE = High; CS = High (Deselect); VIN = VREF
for DQ, DQS, and DM; tCK = tCK (min)
One bank Active; CKE = Low; tCK = tCK (min)
One bank Active; CS = High; CKE = High; Address and
Control inputs change once per clock cycle; DQ, DQS, and
DM change twice per clock cycle; tRC = tRC (max);
One bank Active; BL = 2; Address and Control inputs
change once per clock cycle; tCK = tCK (min); IOUT = 0mA
One bank Active; BL = 2; Address and Control inputs change
once per clock cycle; DQ, DQS, DM change twice per clock
cycle; CKE
tRC = tRFC (min); Input
Input
Four bank interleaved Reads with Auto Precharge; BL = 4;
Address and Controls inputs change per Read, Write, or
Active command; one bank with tRC = tRC (min)
(At T
V
(1,2,3,4,5)
DD
-0.2V;
A
= 0 to +25°C, V
V
(V
Input
IH
DD
= 2.6V +/- 0.1V, T
0.2V
V
Integrated Silicon Solution, Inc. — 1-800-379-4774
DD
IL
or
= V
DDQ
V
IH
= 2.6V, f = 100 MHz)
A
= 0
o
C to +70
Min.
2
2
6
6
o
C)
Max.
3
3
8
8
ISSI
110
140
205
205
200
350
Unit
30
40
55
3
3
pF
pF
pF
pF
Rev. 00A
07/11/05
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
®