DK-DEV-5AGTD7N Altera Corporation, DK-DEV-5AGTD7N Datasheet - Page 41

• Manufacturer Part Number: DK-DEV-5AGTD7N
• Description: Programmable Logic IC Development Tools FPGA Development Kit For 5AGTD7K3F40I3N
• Manufacturer: Altera Corporation
• Type: FPGAr

Specifications of DK-DEV-5AGTD7N

• Rohs: yes
• Product: Development Kits
• Tool Is For Evaluation Of: 5AGTD7K3
• Interface Type: FMC, HSMC, PCIe, USB
• For Use With: 5AGTD7K3

Chapter 6: Board Test System
Using the Board Test System
November 2012 Altera Corporation
Port (FPGA2)
The Port (FPGA2) control allows you to specify which interface to
port tests are available:
■
■
PMA Setting
The PMA Setting button allows you to make changes to the PMA parameters that
affect the active transceiver interface. The following settings are available for analysis:
■
■
■
■
■
Data Type
The Data type control specifies the type of data contained in the transactions. The
following data types are available for analysis:
■
■
■
■
■
■
■
■
■
Bull’s Eye (GXB_R7) (design run at 6.4 Gbps)
SDI (design run at 2.9 Gbps)
Serial Loopback—Routes signals between the receiver and the transmitter. Enter
the following values to enable the serial loopbacks:
0 = high speed serial transceiver signals to loopback on the board
1 = serial loopback
2 = reverse serial loopback pre-CDR
4 = reverse serial loopback post-CDR
VOD—Specifies the voltage output differential of the transmitter buffer.
Pre-emphasis tap
■
■
■
Equalizer—Specifies the setting for the receiver equalizer.
DC gain—Specifies the DC portion of the receiver equalizer.
PRBS7—Selects pseudo-random 7-bit sequences.
PRBS15—Selects pseudo-random 15-bit sequences.
PRBS23—Selects pseudo-random 23-bit sequences.
PRBS31—Selects pseudo-random 31-bit sequences.
HF1—highest frequency divide-by-2 data pattern 10101010.
HF2—next highest frequency divide-by-4 data pattern 1100110011001100.
HF3—second lowest frequency divide-by-8 data pattern 1111000011110000.
LF Bull’s Eye—lowest frequency divide-by-32 data pattern.
LF SDI—lowest frequency divide-by-10 data pattern.
1
Pre—Specifies the amount of pre-emphasis on the pre-tap of the transmitter
buffer.
First post—Specifies the amount of pre-emphasis on the first post tap of the
transmitter buffer.
Second post—Specifies the amount of pre-emphasis on the second post tap of
the transmitter buffer.
Settings HF1, HF2, HF3, LF are for transmit observation only.
Arria V GT FPGA Development Kit
test.
The following
User Guide
6–19