DK-DEV-5AGTD7N Altera Corporation, DK-DEV-5AGTD7N Datasheet - Page 38

• Manufacturer Part Number: DK-DEV-5AGTD7N
• Description: Programmable Logic IC Development Tools FPGA Development Kit For 5AGTD7K3F40I3N
• Manufacturer: Altera Corporation
• Type: FPGAr

Specifications of DK-DEV-5AGTD7N

• Rohs: yes
• Product: Development Kits
• Tool Is For Evaluation Of: 5AGTD7K3
• Interface Type: FMC, HSMC, PCIe, USB
• For Use With: 5AGTD7K3

6–16
Arria V GT FPGA Development Kit
User Guide
Port (FPGA2)
The Port (FPGA2) control allows you to specify which interface to
port tests are available:
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PMA Setting
The PMA Setting button allows you to make changes to the PMA parameters that
affect the active transceiver interface. The following settings are available for analysis:
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Data Type
The Data type control specifies the type of data contained in transceiver transactions.
The following data types are available for transceiver analysis:
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XCVR x4 (HSMB design run at 6.4 Gbps)
CMOS x3 (HSMB design run at 25 Mbps)
FMC XCVR x4 (FMC design run at 6.4 Gbps)
FMC CMOS x80 (FMC design run at 25 Mbps)
Serial Loopback—Routes signals between the receiver and the transmitter. Enter
the following values to enable the serial loopbacks:
0 = high speed serial transceiver signals to loopback on the board
1 = serial loopback
2 = reverse serial loopback pre-CDR
4 = reverse serial loopback post-CDR
VOD—Specifies the voltage output differential of the transmitter buffer.
Pre-emphasis tap
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Equalizer—Specifies the setting for the receiver equalizer.
DC gain—Specifies the DC portion of the receiver equalizer.
PRBS7—Selects pseudo-random 7-bit sequences.
PRBS15—Selects pseudo-random 15-bit sequences.
PRBS23—Selects pseudo-random 23-bit sequences.
PRBS31—Selects pseudo-random 31-bit sequences.
HF1—highest frequency divide-by-2 data pattern 10101010.
HF2—next highest frequency divide-by-4 data pattern 1100110011001100.
HF3—second lowest frequency divide-by-8 data pattern 1111000011110000.
LF FMC—lowest frequency divide-by-40 data pattern.
Pre—Specifies the amount of pre-emphasis on the pre-tap of the transmitter
buffer.
First post—Specifies the amount of pre-emphasis on the first post tap of the
transmitter buffer.
Second post—Specifies the amount of pre-emphasis on the second post tap of
the transmitter buffer.
November 2012 Altera Corporation
Chapter 6: Board Test System
Using the Board Test System
test.
The following