DK-DEV-5AGTD7N Altera Corporation, DK-DEV-5AGTD7N Datasheet - Page 26

• Manufacturer Part Number: DK-DEV-5AGTD7N
• Description: Programmable Logic IC Development Tools FPGA Development Kit For 5AGTD7K3F40I3N
• Manufacturer: Altera Corporation
• Type: FPGAr

Specifications of DK-DEV-5AGTD7N

• Rohs: yes
• Product: Development Kits
• Tool Is For Evaluation Of: 5AGTD7K3
• Interface Type: FMC, HSMC, PCIe, USB
• For Use With: 5AGTD7K3

6–4
Arria V GT FPGA Development Kit
User Guide
The System Info Tab
2. On the Configure menu, click the configure command that corresponds to the
The System Info tab shows the board’s current configuration.
shows the System Info tab. The tab displays the contents of the MAX II registers, the
JTAG chain, the board’s MAC address, and other details stored on the board.
The following sections describe the controls on the System Info tab.
Board Information
The Board information controls display static information about your board.
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MAX II Registers
The MAX II registers control allows you to view and change the current MAX II
register values as described in
take effect immediately. For example, writing a 0 to SRST resets the board.
Table 6–1. MAX II Registers (Part 1 of 2)
System Reset
(SRST)
Page Select Register
(PSR)
functionality you wish to test. The design begins running in the FPGA, and the
corresponding GUI application tabs that interface with the design are now
enabled.
1
Board Name—Indicates the official name of the board, given by the Board Test
System.
Board P/N—Indicates the part number of the board.
Serial number—Indicates the serial number of the board.
Factory test version—Indicates the version of the Board Test System currently
running on the board.
MAX II ver—Indicates the version of MAX II code currently running on the board.
The MAX II code resides in the <install
dir>\kits\arriaVGT_5agtfd7kf40_fpga\examples directory. Newer revisions of
this code might be available on the
Altera website.
MAC—Indicates the MAC address of the board.
Register Name
If you use the Quartus II Programmer for configuration, rather than the
Board Test System GUI, you may need to restart the GUI.
Write only
Read / Write
Read/Write
Capability
Table
Set to 0 to initiate an FPGA reconfiguration.
Determines which of the up to eight (0-7) pages of flash
memory to use for FPGA reconfiguration. The flash memory
ships with pages 0 and 1 preconfigured.
6–1. Changes to the register values with the GUI
Arria V GT FPGA Development Kit
Description
November 2012 Altera Corporation
Figure 6–1 on page 6–1
Chapter 6: Board Test System
Using the Board Test System
page of the