DK-DEV-5AGTD7N Altera Corporation, DK-DEV-5AGTD7N Datasheet - Page 39

• Manufacturer Part Number: DK-DEV-5AGTD7N
• Description: Programmable Logic IC Development Tools FPGA Development Kit For 5AGTD7K3F40I3N
• Manufacturer: Altera Corporation
• Type: FPGAr

Specifications of DK-DEV-5AGTD7N

• Rohs: yes
• Product: Development Kits
• Tool Is For Evaluation Of: 5AGTD7K3
• Interface Type: FMC, HSMC, PCIe, USB
• For Use With: 5AGTD7K3

Chapter 6: Board Test System
Using the Board Test System
November 2012 Altera Corporation
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The following data types are available for CMOS analysis:
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Error Control
This control displays data errors detected during analysis and allows you to insert
errors:
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Loopback
These controls display current transaction performance analysis information collected
since you last clicked Start:
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Start
The Start control initiates transaction performance analysis.
Stop
The Stop control terminates transaction performance analysis.
LF HSMB—lowest frequency divide-by-32 data pattern.
1
PRBS3—Selects pseudo-random 3-bit sequences for HSMB x3 CMOS.
PRBS80—Selects pseudo-random 80-bit sequences for FMC x80 CMOS.
Detected errors—Displays the number of data errors detected in the hardware.
Inserted errors—Displays the number of errors inserted into the transmit data
stream.
Insert Error—Inserts a one-word error into the transmit data stream each time you
click the button. Insert Error is only enabled during transaction performance
analysis.
Clear—Resets the Detected errors and Inserted errors counters to zeros.
Word error rate—Detected word errors/total received words.
TX and RX performance bars—Show the percentage of maximum theoretical data
rate that the requested transactions are able to achieve.
Tx (MBps) and Rx (MBps)—Show the number of bytes of data analyzed per
second.
Settings HF1, HF2, HF3, LF are for transmit observation only.
Arria V GT FPGA Development Kit
User Guide
6–17