DK-DEV-5AGTD7N Altera Corporation, DK-DEV-5AGTD7N Datasheet - Page 27

• Manufacturer Part Number: DK-DEV-5AGTD7N
• Description: Programmable Logic IC Development Tools FPGA Development Kit For 5AGTD7K3F40I3N
• Manufacturer: Altera Corporation
• Type: FPGAr

Specifications of DK-DEV-5AGTD7N

• Rohs: yes
• Product: Development Kits
• Tool Is For Evaluation Of: 5AGTD7K3
• Interface Type: FMC, HSMC, PCIe, USB
• For Use With: 5AGTD7K3

Chapter 6: Board Test System
Using the Board Test System
November 2012 Altera Corporation
f
1
1
Table 6–1. MAX II Registers (Part 2 of 2)
■
■
■
■
Because the System Info tab requires that a specific design is running in the FPGA at
a specific clock speed, writing a 0 to
Board Test System to stop running.
JTAG Chain
The JTAG chain control shows all the devices currently in the JTAG chain. The
Arria V GT Device 1, Arria V GX Device 2, and MAX II are always in the JTAG chain.
SW6 selects whether HSMA, HSMB, and FMC are in the chain. Set the SW6 switch in
the off position to include the interface in the JTAG chain. Refer to
detailed settings.
If you plug in an external USB-Blaster cable to the JTAG header (J1), the On-Board
USB-Blaster II is disabled.
For details on the JTAG chain, refer to the
Reference Manual.
USB-Blaster II
Page Select Override
(PSO)
Page Select Switch
(PSS)
Register Name
PSO—Sets the MAX II PSO register. The following options are available:
■
■
PSR—Sets the MAX II PSR register. The numerical values in the list corresponds to
the page of flash memory to load during FPGA reconfiguration. Refer to
for more information.
PSS—Displays the MAX II PSS register value. Refer to
available options.
SRST—Resets the system and reloads the FPGA with a design from flash memory
based on the other MAX II register values. Refer to
Use PSR—Allows the PSR to determine the page of flash memory to use for
FPGA reconfiguration.
Use PSS—Allows the PSS to determine the page of flash memory to use for
FPGA reconfiguration.
page.
For USB-Blaster II configuration details, refer to the
Read / Write
Read only
Read/Write
Capability
When set to 0, the value in PSR determines the page of
flash memory to use for FPGA reconfiguration. When set to
1, the value in PSS determines the page of flash memory to
use for FPGA reconfiguration.
Holds the current value of the illuminated PGM LED (D12-
D14) based on the following encoding:
■
■
■
SRST,
0 = PGM LED (D14) and corresponds to the flash
memory page for the factory hardware design
1 = PGM LED (D13) and corresponds to the flash
memory page for the user hardware 1 design
2 = PGM LED (D12) and corresponds to the flash
memory page for the user hardware 2 design
Arria V GT FPGA Development Board
or changing the PSO value, can cause the
Table 6–1
Description
Table 6–1
Arria V GT FPGA Development Kit
for more information.
Table 4–3
for the list of
On-Board
Table 6–1
for
User Guide
6–5