XRT83L34ES Exar, XRT83L34ES Datasheet - Page 94
XRT83L34ES
Manufacturer Part Number
XRT83L34ES
Description
Peripheral Drivers & Components - PCIs
Manufacturer
Exar
Datasheet
1.XRT83L34ES.pdf
(99 pages)
Specifications of XRT83L34ES
Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
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XRT83L34
REV. 1.0.1
MICROPROCESSOR INTERFACE I/O TIMING
I
The signals used for the Intel microprocessor interface are: Address Latch Enable (ALE), Read Enable (RD),
Write Enable (WR), Chip Select (CS), Address and Data bits. The microprocessor interface uses minimum ex-
ternal glue logic and is compatible with the timings of the 8051 or 80188 family of microprocessors. The inter-
face timing shown in
F
F
NTEL
IGURE
IGURE
R D Y _D TA C K
A D D R [6:0]
D A TA [7:0]
W R _R /W
A LE _A S
I
R D _D S
NTERFACE
RCLK
RPOS
RNEG
33. R
34. I
or
C S
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
NTEL
ECEIVE
T
t
A
0
IMING
SYNCHRONOUS
t
5
C
Figure 34
LOCK AND
t
1
- A
SYNCHRONOUS
R E A D O P E R A T IO N
V alid A ddress
and
O
R
t
2
UTPUT
DY
P
Figure 36
ROGRAMMED
V alid D ata for R eadback
D
ATA
is described in
T
IMING
I/O I
NTERFACE
91
R
HO
Table
RCLK
T
t
0
IMING
50.
t
5
R
t
3
D ata A vailable to W rite Into the LIU
RCLK
W R IT E O P E R A T IO N
V alid A ddress
t
4
F
xr
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