XRT83L34ES Exar, XRT83L34ES Datasheet - Page 39

• Manufacturer Part Number: XRT83L34ES
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: Exar

Specifications of XRT83L34ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

xr
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TRANSMIT AND RECEIVE TERMINATIONS
The XRT83L34 is a versatile LIU that can be programmed to use one Bill of Materials (BOM) for worldwide
applications for T1, J1 and E1. For specific applications the internal terminations can be disabled to allow the
use of existing components and/or designs.
RECEIVER (CHANNELS 0 - 3)
I
In Hardware mode, RXTSEL (Pin 83) can be tied “High” to select internal termination mode for all receive
channels or tied “Low” to select external termination mode. Individual channel control can only be done in Host
mode. By default the XRT83L34 is set for external termination mode at power up or at Hardware reset.
In Host mode, bit 7 in the appropriate channel register,
Description,” on page
F
If the internal termination mode (RXTSEL = “1”) is selected, the effective impedance for E1, T1 or J1 can be
achieved either with an internal resistor or a combination of internal and external resistors as shown in
N
NTERNAL
IGURE
OTE
RNEG
TNEG
RPO S
TPO S
RCLK
TCLK
: In Hardware mode, pins RXRES[1:0] control all channels.
13. S
R
ECEIVE
IMPLIFIED
Line Driver
T
Equalizer
ERMINATION
TX
RX
64), is set “High” to select the internal termination mode for that specific receive channel.
D
IAGRAM FOR THE
M
ODE
T
ABLE
Channel _n
RXTSEL
R
R
int
int
0
1
6: R
I
NTERNAL
R
int
ECEIVE
TRING
RRING
RTIP
R
TTIP
T
ECEIVE AND
36
ERMINATION
RX TERMINATION
0.68
EXTERNAL
µ
INTERNAL
(Table 21, “Microprocessor Register #1, Bit
F
T
RANSMIT
C
ONTROL
1
4
5
8
1:2
1:1
T1
T2
T
ERMINATION
5
1
8
4
M
ODE
RTIP
RRING
TTIP
TRING
75
110
75
110
Ω
Ω
XRT83L34
Ω
Ω
, 100
, 100
REV. 1.0.1
or 120
or 120
Table
Ω
Ω
Ω
Ω
7.