XRT83L34ES Exar, XRT83L34ES Datasheet - Page 55

• Manufacturer Part Number: XRT83L34ES
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: Exar

Specifications of XRT83L34ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

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QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
OPERATING THE MICROPROCESSOR INTERFACE IN THE INTEL-ASYNCHRONOUS MODE
If the Microprocessor Interface has been configured to operate in the Intel-Asynchronous Mode, then the
following Microprocessor Interface pins will assume the role that is described below in Table 17.
T
RDY_DTACK* Active Low READY Output pin - RDY:
ABLE
WR*/R/W*
P
RD*/DS*
ALE/AS
IN
N
17: T
AME
HE
Address Latch Enable - ALE:
If the Microprocessor Interface has been configured to operate in
the Intel-Asynchronous Mode, then this active-high input pin is
used to latch the data (residing on the Address Bus, A[6:0]) into the
MIcroprocessor Interface circuitry of the XRT83L34 device and to
indicate the start of a READ or WRITE cycle.
Pulling this input pin "HIGH" enables the input bus drivers for the
Address Bus input pins. The contents of the Address Bus will be
latched into the Microprocessor Interface circuitry upon the falling
edge of this input signal.
Read Strobe Input - RD*:
If the Microprocessor Interface is operating in the Intel-Asynchro-
nous Mode, then this input pin will function as the RD* (Active-Low
READ Strobe) input signal from the Microprocessor. Once this
active-low signal is asserted, then the XRT83L34 device will place
the contents of the addressed register on the Microprocessor Inter-
face Bi-Directional Data Bus (D[7:0]). When this signal is negated,
then the Bi-Directional Data Bus will be tri-stated.
If the Microprocessor Interface has been configured to operate in
the Intel-Asynchronous Mode, then this output pin will function as
the "active-low" READY output.
During a READ or WRITE cycle, the Microprocessor Interface
block will toggle this output pin to the logic "LOW" level, ONLY
when it (the Microprocessor Interface) is ready to complete or ter-
minate the current READ or WRITE cycle. Once the Microproces-
sor has determined that this input pin has toggled to the logic
"LOW" level, then it is now safe for it to move on and execute the
next READ or WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor Interface
block is holding this output pin at a logic "HIGH" level, then the
Microprocessor is expected to extend this READ or WRITE cycle,
until it detects this output pin being toggled to the logic "LOW"
level.
Write Strobe Input - WR*:
If the Microprocessor Interface is configured to operate in the Intel-
Asynchronous Mode, then this input pin functions as the WR*
(Active LOW WRITE Strobe) input signal from the Microprocessor.
Once this active-low signal is asserted, then the input buffers
(associated with the Bi-Directional Data bus, D[7:0]) will be
enabled. The Microprocessor Interface will latch the contents on
the Bi-Directional Data Bus (into the "target" register or address
location, within the XRT83L34 device) upon the rising edge of this
input pin.
R
OLES OF THE
V
ARIOUS
THE
M
D
ESCRIPTION
ICROPROCESSOR
I
NTEL
-A
SYNCHRONOUS
52
I
NTERFACE
M
ODE
P
INS
,
WHEN CONFIGURED TO OPERATE IN
T
YPE
O
I
I
I
P
IN
XRT83L34
/B
71
70
73
69
REV. 1.0.1
ALL