XRT83L34ES Exar, XRT83L34ES Datasheet - Page 49

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XRT83L34ES

Manufacturer Part Number
XRT83L34ES
Description
Peripheral Drivers & Components - PCIs
Manufacturer
Exar
Datasheet

Specifications of XRT83L34ES

Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
xr
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
LOOP-BACK MODES
The XRT83L34 supports several Loop-Back modes under both Hardware and Host control. In Hardware
mode the two LOOP[1:0] pins control the Loop-Back functions for each channel independently according to
Table
In Host mode the Loop-Back functions are controlled by the three LOOP[2:0] interface bits. Each channel can
be programmed independently according to
LOCAL ANALOG LOOP-BACK (ALOOP)
With Local Analog Loop-Back activated, the transmit data at TTIP and TRING are looped-back to the analog
input of the receiver. External inputs at RTIP/RRING in this mode are ignored while valid transmit data
continues to be sent to the line. Local Analog Loop-Back exercises most of the functional blocks of the
XRT83L34 including the jitter attenuator which can be selected in either the transmit or receive paths. Local
Analog Loop-Back is shown in
In this mode, the jitter attenuator (if selected) can be placed in the transmit or receive path.
14.
F
IGURE
RPOS
RNEG
TNEG
TPOS
RCLK
TCLK
20. L
T
ABLE
LOOP2
OCAL
Figure
T
ABLE
0
1
1
1
1
LOOP1
Encoder
Decoder
14: L
A
0
0
1
1
20.
NALOG
15: L
OOP
LOOP1
OOP
Table
-
X
0
0
1
1
L
BACK CONTROL IN
OOP
JA
-
BACK CONTROL IN
15.
-
Recovery
LOOP0
BACK SIGNAL FLOW
Data &
Clock
46
LOOP0
0
1
0
1
X
0
1
0
1
Timing
Control
H
L
L
ARDWARE MODE
OOP
OOP
H
Rx
OST MODE
Remote
Remote
-
Analog
-
Analog
Digital
Digital
BACK
None
BACK
None
Dual
Tx
M
M
ODE
ODE
TTIP
TRING
RTIP
RRING
XRT83L34
REV. 1.0.1

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