XRT83L34ES Exar, XRT83L34ES Datasheet - Page 76

• Manufacturer Part Number: XRT83L34ES
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: Exar

Specifications of XRT83L34ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83L34
REV. 1.0.1
R
EGISTER
0000110
0010110
0100110
0110110
B
D7
D6
D5
D4
D3
D2
D1
D0
IT
A
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
#
DDRESS
C
C
C
C
C
QRPDIS_n
NLCDIS_n
RLOSIS_n
DMOIS_n
AISDIS_n
Reserved
FLSIS_n
LCVIS_n
HANNEL
HANNEL
HANNEL
HANNEL
HANNEL
N
AME
T
ABLE
_n
_0
_1
_2
_3
26: M
Driver Monitor Output Interrupt Status: This bit is set to a
“1” every time the DMO status has changed since last read.
N
FIFO Limit Interrupt Status: This bit is set to a “1” every time
when FIFO Limit (Read/Write pointer with +/- 3 bits apart) sta-
tus has changed since last read.
N
Line Code Violation Interrupt Status: This bit is set to a “1”
every time when LCV status has changed since last read.
N
Network Loop-Code Detection Interrupt Status: This bit is
set to a “1” every time when NLCD status has changed since
last read.
N
AIS Detection Interrupt Status: This bit is set to a “1” every
time when AISD status has changed since last read.
N
Receive Loss of Signal Interrupt Status: This bit is set to a
“1” every time RLOS status has changed since last read.
N
Quasi-Random Pattern Detection Interrupt Status: This bit
is set to a “1” every time when QRPD status has changed
since last read.
N
OTE
OTE
OTE
OTE
OTE
OTE
OTE
ICROPROCESSOR
: This bit is reset upon read.
: This bit is reset upon read.
: This bit is reset upon read.
: This bit is reset upon read.
: This bit is reset upon read.
: This bit is reset upon read.
: This bit is reset upon read.
73
R
EGISTER
F
UNCTION
#6, B
IT
D
ESCRIPTION
R
EGISTER
xr
T
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RO
YPE
R
V
ALUE
ESET
0
0
0
0
0
0
0
0