XRT83L34ES Exar, XRT83L34ES Datasheet - Page 73

• Manufacturer Part Number: XRT83L34ES
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: Exar

Specifications of XRT83L34ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

xr
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
R
EGISTER
0000100
0010100
0100100
0110100
B
D7
D6
D5
D4
D3
D2
D1
D0
IT
A
#
DDRESS
C
C
C
C
C
QRPDIE_n
NLCDIE_n
RLOSIE_n
DMOIE_n
AISDIE_n
Reserved
LCVIE_n
HANNEL
FLSIE_n
HANNEL
HANNEL
HANNEL
HANNEL
N
AME
T
ABLE
_n
_0
_1
_2
_3
24: M
DMO Interrupt Enable: Writing a “1” to this bit enables DMO
interrupt generation, writing a “0” masks it.
FIFO Limit Status Interrupt Enable: Writing a “1” to this bit
enables interrupt generation when the FIFO limit is within to 3
bits, writing a “0” to masks it.
Line Code Violation Interrupt Enable: Writing a “1” to this bit
enables Line Code Violation interrupt generation, writing a “0”
masks it.
Network Loop-Code Detection Interrupt Enable: Writing a
“1” to this bit enables Network Loop-code detection interrupt
generation, writing a “0” masks it.
AIS Interrupt Enable: Writing a “1” to this bit enables Alarm
Indication Signal detection interrupt generation, writing a “0”
masks it.
Receive Loss of Signal Interrupt Enable: Writing a “1” to this
bit enables Loss of Receive Signal interrupt generation, writing
a “0” masks it.
QRSS Pattern Detection Interrupt Enable: Writing a “1” to
this bit enables QRSS pattern detection interrupt generation,
writing a “0” masks it.
ICROPROCESSOR
70
R
EGISTER
F
UNCTION
#4, B
IT
D
ESCRIPTION
R
EGISTER
T
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
YPE
XRT83L34
REV. 1.0.1
R
V
ALUE
ESET
0
0
0
0
0
0
0
0