XRT83L34ES Exar, XRT83L34ES Datasheet - Page 56

• Manufacturer Part Number: XRT83L34ES
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: Exar

Specifications of XRT83L34ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83L34
REV. 1.0.1
CONFIGURING THE MICROPROCESSOR INTERFACE TO OPERATE IN THE INTEL-ASYNCHRONOUS
MODE
The user can configure the Microprocessor Interface to operate in the Intel-Asynchronous Mode by tying the
UPTS1 (Pin 106) to GND.
Finally, if the Microprocessor Interface has been configured to operate in the Intel-Asynchronous Mode, then it
will perform READ and WRITE operations as described below.
THE INTEL-ASYNCHRONOUS READ CYCLE
If the Microprocessor Interface (of the XRT83L34 device) has been configured to operate in the Intel-
Asynchronous Mode, then the Microprocessor should do all of the following, anytime it wishes to read out the
contents of a register.
Figure 25 presents a timing diagram that illustrates the behavior of the Microprocessor Interface signals, during an "Intel-
1. Place the address of the "target" register (within the XRT83L34 device) on the Address Bus input pins,
2. While the Microprocessor is placing this address value on the Address Bus, the Address Decoding circuitry
3. Toggle the ALE/AS (Address Latch Enable) input pin "HIGH". This step enables the "Address Bus" input
4. After allowing the data on the Address Bus pins to settle (by waiting the appropriate "Address Data Setup
5. Next, the Microprocessor should indicate that this current bus cycle is a "READ" operation by toggling the
6. Immediately after the Microprocessor toggles the "Read Strobe" (RD*/DS*) signal "low", the XRT83L34
7. After some settling time, the data on the "Bi-Directional" data bus will stabilize and can be read by the
8. After the Microprocessor detects the RDY*/DTACK* signal (from the XRT83L34 device) toggling "LOW", it
A[6:0].
(within the user’s system) should assert the CS* (Chip Select) input pin of the XRT83L34 device, by tog-
gling it "LOW". This action enables further communication between the Microprocessor and the XRT83L34
Microprocessor Interface block
drivers, within the Microprocessor Interface block of the XRT83L34 device.
time"), the Microprocessor should toggle the ALE/AS input pin "LOW". This step causes the XRT83L34
device to "latch" the contents of the "Address Bus" into its internal circuitry. At this point, the address of the
register (within the XRT83L34 device) has now been selected.
"RD*/DS*" (Read Strobe) input pin "LOW". This action also enable the bi-directional data bus output driv-
ers of the XRT83L34 device. At this point, the "Bi-Directional" Data Bus output drivers will proceed to drive
the contents of the "latched" addressed onto the bi-directional data bus, D[7:0].
device will continue to drive the RDY*/DTACK* output pin "high". The XRT83L34 device does this in order
to inform the Microprocessor that the data (to be read from the data bus) is "NOT READY" to be "latched"
into the Microprocessor. In this case, the Microprocessor should continue to hold the "Read Strobe" (RD*/
DS*) signal "LOW" until it detects the "RDY*/DTACK*" output pin toggling "LOW".
Microprocessor. At this time, the XRT83L34 device will indicate that this data can be read by toggling the
RDY*/DTACK* (READY) signal "LOW".
can then terminate the READ cycle by toggling the RD*/DS* (READ Strobe) input pin "HIGH".
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
53
xr