DS3172 Maxim Integrated, DS3172 Datasheet - Page 61

• Manufacturer Part Number: DS3172
• Description: Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
• Manufacturer: Maxim Integrated

Specifications of DS3172

• Part # Aliases: 90-31720-000

The external RST pin and the global reset bit in the global configuration register (GL.CR1.RST) are combined to
create an internal global reset signal. The global reset signal resets all the status and control registers on the chip,
except the GL.CR1.RST bit, to their default values and resets all the other flops in the global logic and ports to their
reset values. The processor bus output signals are also forced to be HIZ when the RST pin is active (low). The
global reset bit (GL.CR1.RST) stays set after a one is written to it, but is reset to zero when the external RST pin is
active or when a zero is written to it.
At the port level, the global reset signal combines with the port-reset bit in the port control register
(PORT.CR1.RST) to create a port-reset signal. The port reset signal resets all the status and control registers on
the port to their default values and resets all the other flops, except PORT.CR1.RST, to their reset values. The port
reset bit (PORT.CR1.RST) stays set after a one is written to it, but is reset to zero when the global reset signal is
active or when a zero is written to it.
The data path reset function is a little different from the “general” reset function. The data path reset signal does not
reset the control register bits, but it does reset all of the status registers, counters and flops, the “general” reset
signal resets everything including the control register bits, excluding the reset bit. All clocks are functional, being
controlled by configuration bits, while data path reset is active. The LIU and CLAD circuits will be operating
normally during data path reset, which allows the internal phase locked loops to settle as quickly as possible. The
LIU will be sending all zeros (LOS) since data path reset will be forcing the transmit TPOSn and TNEGn to logic
zero. (NOTE: The BERT data path and control registers are reset when the global data path reset or the port data
path reset or the port power-down signal is active.)
The global data path reset bit (GL.CR1.RSTDP) gets set to one when the global reset signal is active. The port
data path reset bit (PORT.CR1.RSTDP) and the port power-down bit (PORT.CR1.PD) bit get set to one when the
global reset signal is active or the port reset signal is active. These control bits will be cleared when a zero is
written to them if the global reset signal or the port-reset signal is not active. The global data path reset signal is
active when the global data path reset bit is set. The port data path reset signal is active when either the global
data path reset bit or the port data path reset bit is set. The port power-down signal is active when the port power-
down bit is set.
Figure 10-5. Reset Sources
NOTE: Assumes
active high signals
RST pin
D
D
SET
CLR
SET
CLR
Q
Q
Q
Q
GL.CR1 . RSTDP
GL.CR1 . RST
61
PORT.CR1 .
RSTDP
D
D
D
PORT.CR1 . PD
SET
CLR
SET
CLR
SET
CLR
Q
Q
Q
Q
Q
Q
PORT.CR1 .
RST
Port Data Path Reset
Global Reset
Port Reset
Global Data Path Reset
Port Power Down