DS3172 Maxim Integrated, DS3172 Datasheet - Page 101

• Manufacturer Part Number: DS3172
• Description: Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
• Manufacturer: Maxim Integrated

Specifications of DS3172

• Part # Aliases: 90-31720-000

highest numbered bit (7), and the LSB is stored in the lowest numbered bit (0). This is to differentiate between a
byte in a register and the corresponding byte in a signal.
10.8.8 Receive Trail Trace Processing
The Receive Trail Trace Processing accepts an incoming data line and performs trail trace alignment, trail trace
extraction, expected trail trace comparison, and bit reordering. If receive data inversion is enabled, the incoming
data is inverted before trail trace processing is performed. Receive data inversion is programmable (on or off).
Trail trace alignment determines the trail trace identifier boundary by identifying the multi-frame alignment signal.
The multi-frame alignment signal (MAS) is located in the MSB of each byte (see
each checked for the multi-frame alignment start bit, which is a one. Once a multi-frame alignment start bit is found,
the remaining fifteen bits of the MAS are verified as being zero. The MAS check is performed one byte at a time.
Multi-frame alignment is programmable (on or off). When multi-frame alignment is disabled, the incoming bytes are
sequentially stored starting with a random byte.
Figure 10-22. Trail Trace Byte (DT = Trail Trace Data)
Trail trace extraction extracts the trail trace identifier from the incoming trail trace data stream, generates a trail
trace identifier change indication, detects a trail trace identifier idle (Idle) condition, and detects a trail trace
identifier unstable (TIU) condition. The trail trace identifier bytes are stored sequentially with the first byte (MAS
equals 1 if trail trace alignment is enabled) being stored in the first byte of memory. If the exact same non-zero trail
trace identifier is received five consecutive times and it is different from the receive trail trace identifier, a receive
trail trace identifier update is performed, and the receive trail trace identifier change indication is set.
An Idle condition is declared when an all zeros trail trace identifier is received five consecutive times. An Idle
condition is terminated when a non-zero trail trace identifier is received five consecutive times or a TIU condition is
declared. A TIU condition is declared if eight consecutive trail trace identifiers are received that do not match either
the receive trail trace identifier or the previously stored current trail trace identifier. The TIU condition is terminated
when a non-zero trail trace identifier is received five consecutive times or an Idle condition is declared.
Expected trail trace comparison compares the received and expected trail trace identifiers. The comparison is a 7-
bit comparison of the seven least significant bits (DT[2:8] (see
multi-frame alignment signal is ignored). If the received and expected trail trace identifiers do not match, a trail
trace identifier mismatch (TIM) condition is declared. If they do match the TIM condition is terminated. The 16-byte
expected trail trace identifier is programmable. Expected trail trace comparison is programmable (on or off). If multi-
frame alignment is disabled, expected trail trace comparison is disabled. Immediately after a reset, the receive trail
trace identifier is invalid. All comparisons between the receive trail trace identifier and expected trail trace identifier
will match (a TIM condition cannot occur) until after the first receive trail trace identifier update occurs.
Bit reordering changes the bit order of each byte. If bit reordering is disabled, the incoming 8-bit data stream
DT[1:8] with DT[1] being the MSB and DT[8] being the LSB is output to the Receive Data Storage with the MSB in
RTD[7] and the LSB in RTD[0] of the receive trace ID data RTD[7:0]. If bit reordering is enabled, the incoming 8-bit
data stream DT[1:8] is output to the Receive Data Storage with the MSB in RTD[0] and the LSB in RTD[7] of the
receive trace ID data RTD[7:0]. DT[1] is the first bit received from the incoming data stream.
Once all of the trail trace processing has been completed, The 8-bit parallel data stream is passed on to the
Receive Data Storage.
10.8.9 Receive Data Storage
The Receive Data Storage block contains memory for 48 bytes of data, maintains data status information, and has
controller circuitry for reading and writing the memory. The Receive Data Storage controller functions include filling
MAS or
DT[1]
Bit 1
MSB
DT[2]
Bit 2
DT[3]
Bit 3
DT[4]
Bit 4
DT[5]
Bit 5
101
DT[6]
Bit 6
Figure
10-22) of each trail trace identifier byte (The
DT[7]
Bit 7
DS3171/DS3172/DS3173/DS3174
Figure
DT[8]
Bit 8
LSB
10-22). The MAS bits are