DS3172 Maxim Integrated, DS3172 Datasheet - Page 32

• Manufacturer Part Number: DS3172
• Description: Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
• Manufacturer: Maxim Integrated

Specifications of DS3172

• Part # Aliases: 90-31720-000

PIN NAME
RSOFOn /
TSOFOn /
RCLKOn /
RGCLKn
RSERn
RDENn
TDENn
TYPE
O
O
O
O
Framer Start Of Frame / Data Enable
See
TSOFOn: When the port framer is configured for the DS3 or E3 framed modes and the
TSOFOn pin function is selected, this signal is used to indicate the start of the DS3/E3 frame on
the TSERn pin. This signal pulses high three clocks before the first overhead bit in a DS3 or E3
frame that will be input on TSERn. The signal is updated on the positive clock edge of the
referenced clock pin if the clock pin signal is not inverted, otherwise it is updated on the falling
edge of the clock. The signal is typically referenced to the TCLKIn transmit clock input pins, but
it can be referenced to the TLCLKn, TCLKOn, RCLKOn and RLCLKn clock pins.
This signal can be inverted.
TDENn: When the port framer is configured for the DS3 or E3 framed modes and the TDENn
pin function is selected, this signal is used to mark the DS3/E3 frame bits on the TSERn pin.
The signal goes high three clocks before the start of DS3/E3 payload bits and goes low three
clocks before the end of the DS3/E3 payload bits. The signal is updated on the positive clock
edge of the referenced clock pin if the clock pin signal is not inverted, otherwise it is updated on
the falling edge of the clock. The signal is typically referenced to the TCLKIn transmit clock
input pins, but it can be referenced to the TLCLKn, TCLKOn, RCLKOn and RLCLKn clock pins.
This signal can be inverted.
Receive Serial Data
RSERn: When the port framer is configured for the DS3 or E3 framed modes, this pin outputs
the receive data signal from the LIU or receive line pins. The signal is updated on the positive
clock edge of the referenced clock pin if the clock pin signal is not inverted, otherwise it is
updated on the falling edge of the clock. The signal is typically referenced to the RCLKOn
receive clock output pin, but it can be referenced to the RGCLKn and RLCLKn clock pins.
This signal can be inverted
o
o
Receive Clock Output / Gapped Clock
See
RCLKOn: When the port framer is configured for the DS3 or E3 framed modes and RCLKOn is
selected, this clock output signal is active. It is the same as the internal receive framer clock.
This clock is typically used for the reference clock for the RSERn, RSOFOn / RDENn signals
but can also be used as the reference for the RPOSn / RDATn, RNEGn / RLCVn, TSOFIn,
TSERn, TSOFOn / TDENn, TPOSn / TDATn and TNEGn signals.
This signal can be inverted.
o
o
RGCLKn: When the port is configured for DS3/E3 framed mode and RGCLKn is selected, this
gated clock output signal is active. It is the same as the internal receive framer clock gated by
RDENn. This clock is typically used for the reference clock for the RSERn.
This signal can be inverted
Receive Framer Start Of Frame /Data Enable
See
RSOFOn: When the port framer is configured for the DS3 or E3 framed modes and the
RSOFOn pin function is enabled, this signal is used to indicate the start of the DS3/E3 frame.
This signal indicates the first DS3/E3 overhead bit on the RSERn pin when high. The signal is
updated on the positive clock edge of the referenced clock pin if the clock pin signal is not
inverted, otherwise it is updated on the falling edge of the clock. The signal is typically
referenced to the RCLKOn receive clock output pin, but it can be referenced to the RLCLKn
clock input pin.
This signal can be inverted.
RDENn: When the port framer is configured for the DS3 or E3 framed modes and the RDENn
pin function is enabled, this signal is used to indicate the DS3/E3 payload bit positions of the
data on the RSERn pin. The signal goes high during each DS3/E3 payload bit and goes low
during each DS3/E3 overhead bit. The signal is updated on the positive clock edge of the
referenced clock pin if the clock pin signal is not inverted, otherwise it is updated on the falling
edge of the clock. The signal is typically referenced to the RCLKOn receive clock output pin,
but it can be referenced to the RLCLKn clock input pin.
This signal can be inverted.
DS3: 44.736 Mbps +20ppm
E3: 34.368 Mbps +20ppm
DS3: 44.736 MHz +20 ppm
E3: 34.368 MHz +20 ppm
Table 10-21.
Table 10-24.
Table 10-23.
32
PIN DESCRIPTION