DS3172 Maxim Integrated, DS3172 Datasheet - Page 137

• Manufacturer Part Number: DS3172
• Description: Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
• Manufacturer: Maxim Integrated

Specifications of DS3172

• Part # Aliases: 90-31720-000

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 13: Receive Clock Output Select (RCLKS). This bit is used to select the function of the RGCLKn / RCLKOn
pins. See
Bit 12: Receive Start Of Frame Output Select (RSOFOS). This bit is to select the function of the RSOFOn /
RDENn pins. See
Bit 10: Transmit Clock Output Select (TCLKS). This bit is used to select the function of the TGCLKn / TCLKOn
pins. See
Bit 9: Transmit Start Of Frame Output Select (TSOFOS). This bit is used to select the function of the TSOFOn /
TDENn pins. See
Bits 7 to 6: Port 8 kHz Reference Source Select (P8KRS[1:0]). This bit selects the source of the 8 kHz reference
from the port sources. The 8K reference for this port can be used as the global 8K reference source. See
10-13.
Bit 6: Port 8 kHz Reference Source Select (P8KRS). This bit selects the source of the 8 kHz reference from the
port sources. The 8K reference for this port can also be used as the global 8K reference source.
Bit 5: PORT 8 kHz Reference Source (P8KREF). This bit selects the source of the 8 kHz reference for PLCP
trailer operation and one second timer.
Bit 4: LOOP Time Enable (LOOPT). When this bit is set, the port is in loop time mode. The transmit clock is set to
the receive clock from the RLCLKn pin or the recovered clock from the LIU or the CLAD clock and the TCLKIn pin
is not used. This function of this bit is conditional on other control bits. See
Bit 3: CLAD Transmit Clock Source Control (CLADC). This bit is used to enable the CLAD clocks as the source
of the internal transmit clock. This function of this bit is conditional on other control bits. See
details.
Bit 2: Receive Framer IO Signal Timing Select (RFTS). This bit controls the timing reference for the signals on
the receive framer interface IO pins. The pins controlled are RSERn, RSOFOn / RDENn. See
details.
0 = Selects the RGCLKn signal, or the drive low pin function.
1 = Selects RCLKOn signal.
0 = Selects RDENn signal.
1 = Selects RSOFOn signal.
0 = Selects TGCLKn signal.
1 = Selects TCLKOn signal.
0 = Selects TDENn signal.
1 = Selects TSOFOn signal.
0 = Selects the receive internal framer clock (based on RLCLKn or RX LIU recovered clock
1 = Selects the transmit internal framer clock (based on TCLKIn or the CLAD clock)
0 = 8 kHz reference from global source
1 = 8 kHz reference from this ports selected source
0 = Normal transmit clock operation
1 = Transmit using the receive clock
0 = Use CLAD clocks for the transmit clock as appropriate
1 = Do not use CLAD clocks for the transmit clock – (if no loopback is enabled, TCLKIn is the source)
Table
Table
P8KRS1
15
--
0
7
0
10-24.
10-22.
Table 10-21.
Table
10-23.
P8KRS0
14
--
0
6
0
PORT.CR3
Port Control Register 3
(0,2,4,6)44h
P8KREF
RCLKS
13
0
5
0
RSOFOS
LOOPT
12
0
0
4
137
RESERVED
CLADC
11
0
3
0
Table 10-4
TCLKS
RFTS
10
0
2
0
for more details.
TSOFOS
TFTS
9
0
1
0
Table 10-4
Table 10-8
RESERVED
TLTS
for more
for more
8
0
0
0
Table