DS3172 Maxim Integrated, DS3172 Datasheet - Page 173

• Manufacturer Part Number: DS3172
• Description: Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
• Manufacturer: Maxim Integrated

Specifications of DS3172

• Part # Aliases: 90-31720-000

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 11 to 8: Expected Trail Trace Identifier Address (ETIA[3:0]) – These four bits indicate the expected trail
trace identifier byte to be read/written by the next memory access. Address 0h indicates the first byte of the
expected trail trace identifier. Note: The value of these bits increments with each expected trail trace identifier
memory access (when these bits are Fh, a memory access will return them to 0h).
Bits 3 to 0: Receive Trail Trace Identifier Address (RTIA[3:0]) – These four bits indicate the receive trail trace
identifier byte to be read by the next memory access. Address 0h indicates the first byte of the receive trail trace
identifier. Note: The value of these bits increments with each received trail trace identifier memory access (when
these bits are Fh, a memory access will return them to 0h).
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 2: Receive Trail Trace Identifier Mismatch (RTIM)
Bit 1: Receive Trail Trace Identifier Unstable (RTIU)
Bit 0: Receive Trail Trace Identifier Idle (RIDL)
0 = Received and expected trail trace identifiers match.
1 = Received and expected trail trace identifiers do not match; trail trace identifier
mismatch (TIM) declared.
0 = Received trail trace identifier is not unstable
1 = Received trail trace identifier is in an unstable condition (TIU); TIU is declared when eight
consecutive trail trace identifiers are received that do not match either the receive trail trace
identifier or the previously stored current trail trace identifier.
0 = Received trail trace identifier is not in idle condition.
1 = Received trail trace identifier is in idle condition. Idle condition is declared upon the reception of
an all zeros trail trace identifier five consecutive times.
15
15
--
--
--
--
0
7
0
7
14
14
--
--
--
--
0
6
0
6
TT.RTIAR
Trail Trace Receive Identifier Address Register
(0,2,4,6)F2h
TT.RSR
Trail Trace Receive Status Register
(0,2,4,6)F4h
Reserved
Reserved
13
13
--
--
0
5
0
5
Reserved
Reserved
12
12
--
0
0
--
4
4
173
ETIA3
RTIA3
11
11
--
--
0
3
0
3
RTIA2
ETIA2
RTIM
10
10
--
0
2
0
2
ETIA1
RTIA1
RTIU
--
9
0
1
0
9
1
ETIA0
RTIA0
RIDL
--
8
0
0
0
8
0