DS3172 Maxim Integrated, DS3172 Datasheet - Page 132

• Manufacturer Part Number: DS3172
• Description: Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
• Manufacturer: Maxim Integrated

Specifications of DS3172

• Part # Aliases: 90-31720-000

Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 1 : CLAD Loss of Lock (CLOL) – This bit is set when any of the PLLs in the CLAD are not locked to the
reference frequency.
Bit 0: Global Performance Monitoring Update Status (GPMS) This bit is set when all of the port performance
register update status bits (PORT.SR.PMS), that are enabled for global update control (PORT.CR1.PMUM=1), are
set. It is an “AND” of all the globally enabled port PMU status bits. In global software update mode, the global
update request bit (GL.CR1.GPMU) should be held high until this status bit goes high.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 4: 8K Reference Activity Status Latched (8KREFL) This bit will be set when the 8 kHz reference signal on
the GPIO4 pin is active. The GL.CR2.G8KIS bit must be set for the activity to be monitored.
Bit 3: CLAD Reference Clock Activity Status Latched (CLADL) This bit will be set when the CLAD PLL
reference clock signal on the CLKA pin is active.
Bit 2: One Second Status Latched (ONESL) This bit will be set once a second. The GL.ISR.GSR status bit will
be set when this bit is set and the GL.SRIE.ONESIE bit is enabled. The INT pin will be driven low if this bit is set
and the GL.SRIE.ONESIE bit and the GL.ISRIE.GSRIE bit are enabled.
Bit 1: CLAD Loss Of Lock Latched (CLOLL) This bit will be set when the GL.SR.CLOL status bit changes from
low to high. The GL.ISR.GSR bit will be set when this bit is set and the GL.SRIE.CLOLIE bit is set and the INT pin
will be driven low if the GL.ISRIE.GSRIE bit is also enabled.
Bit 0: Global Performance Monitoring Update Status Latched (GPMSL) This bit will be set when the
GL.SR.GPMS status bit changes from low to high. This bit will set the GL.ISR.GSR status bit if the
GL.SRIE.GPMSIE is enabled. This bit will drive the interrupt pin low if the GL.SRIE.GPMSIE bit and the
GL.ISRIE.GSRIE bit are enabled.
0 = The associated update request signal is low or not all register updates are completed
1 = The requested performance register updates are all completed
15
15
--
--
--
--
7
7
14
14
--
--
--
--
6
6
GL.SR
Global Status Register
014h
GL.SRL
Global Status Register Latched
016h
13
13
--
--
--
--
5
5
8KREFL
12
12
--
--
--
4
4
132
CLADL
11
11
--
--
--
3
3
ONESL
10
10
--
--
--
2
2
CLOLL
CLOL
--
--
9
1
9
1
GPMSL
GPMS
--
--
8
0
8
0