DS3172 Maxim Integrated, DS3172 Datasheet - Page 170

• Manufacturer Part Number: DS3172
• Description: Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
• Manufacturer: Maxim Integrated

Specifications of DS3172

• Part # Aliases: 90-31720-000

12.8 Trail Trace
12.8.1 Trail Trace Transmit Side
The transmit side utilizes three registers. Register Map
Table 12-21. Transmit Side Trail Trace Register Map
12.8.1.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 3: Transmit Multi-frame Alignment Insertion Disable (TMAD) – When 0, multi-frame alignment signal (MAS)
insertion is enabled, and the first bit transmitted of each trail trace byte is overwritten with an MAS bit. When 1,
MAS insertion is disabled, and the trail trace bytes from the Transmit Data Storage are output without being
modified.
Bit 2: Transmit Trail Trace Identifier Idle (TIDLE) – When 0, the programmed transmit trail trace identifier will be
transmitted. When 1, all zeros will be transmitted.
Bit 1: Transmit Data Inversion Enable (TDIE) – When 0, the outgoing data from trail trace processing is output
directly. When 1, the outgoing data from trail trace processing is inverted before being output.
Bit 0: Transmit Bit Reordering Enable (TBRE) – When 0, bit reordering is disabled (The first bit transmitted is the
MSB TT.TIR.TTD[7] of the byte). When 1, bit reordering is enabled (The first bit transmitted is the LSB
TT.TIR.TTD[0] of the byte).
(0,2,4,6)EAh TT.TTIAR
(0,2,4,6)ECh TT.TIR
(0,2,4,6)EEh
(0,2,4,6)E8h TT.TCR
Address
15
--
--
0
7
0
Register
--
14
--
--
0
6
0
TT.TCR
Trail Trace Transmit Control Register
(0,2,4,6)E8h
Trail Trace Transmit Control Register
Trail Trace Transmit Identifier Address Register
Trail Trace Transmit Identifier Register
Unused
Register Description
13
--
--
0
5
0
Reserved
12
--
0
0
4
170
TMAD
11
--
0
3
0
TIDLE
10
--
0
2
0
TDIE
--
9
0
1
0
TBRE
--
8
0
0
0