DS3172 Maxim Integrated, DS3172 Datasheet - Page 14

• Manufacturer Part Number: DS3172
• Description: Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
• Manufacturer: Maxim Integrated

Specifications of DS3172

• Part # Aliases: 90-31720-000

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3.5 Transmit DS3/E3 LIU Features
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3.6 Jitter Attenuator Features
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3.7 Clock Rate Adapter Features
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3.8 HDLC Overhead Controller Features
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3.9 FEAC Controller Features
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FEAC port for DS3 FEAC channel can be configured to send one codeword, one codeword continuously, or
two different codewords back-to-back to send DS3 Line Loopback commands
16-byte Trail Trace Buffer port for the G.832 trail access point identifier
Insertion of G.832 payload type, and timing marker bits from registers
DS3 M23 C bits configurable as payload or overhead, as overhead they can be controlled from registers or the
transmit overhead port
Most framing overhead fields can be sourced from transmit overhead port
Formatter bypass mode for clear channel or externally defined format applications
Wide 50+20% transmit clock duty cycle
Line Build-Out (LBO) control
Tri-state line driver outputs support protection switching applications
Per-channel power-down control
Output driver monitor status indication
Fully integrated and requiring no external components
Can be placed in transmit or receive path
FIFO depth of 16 bits
Standard compliant transmission jitter and wander
Generation of the internally needed DS3 (44.736 MHz) and E3 (34.368 MHz) clocks a from single input
reference clock
Input reference clock can be 51.84 MHz, 44.736MHz or 34.368 MHz
Internally derived clocks can be used as references for LIU and jitter attenuator
Derived clocks can be transmitted off-chip for external system use
Standards compliant jitter and wander requirements.
Each port has a dedicated HDLC controller for DS3/E3 framer link management
256-byte receive and transmit FIFOs
Handles all of the normal Layer 2 tasks including zero stuffing/de-stuffing, FCS generation/checking, abort
generation/checking, flag generation/detection, and byte alignment
Programmable high and low water marks for the transmit and receive FIFOs
Terminates the Path Maintenance Data Link in DS3 C-bit Parity mode and optionally the G.751 Sn bit or the
G.832 NR or GC channels
RX data is forced to all ones during LOS, LOF and AIS detection to eliminate false packets
Each port has a dedicated FEAC controller for DS3/E3 link management
Designed to handle multiple FEAC codewords without Host intervention
Receive FEAC automatically validates incoming codewords and stores them in a 4-byte FIFO
Transmit FEAC can be configured to send one codeword, one codeword continuously, or two different
codewords back-to-back to send DS3 Line Loopback commands
Terminates the FEAC channel in DS3 C-Bit Parity mode and optionally the Sn bit in E3 mode
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