DS3172 Maxim Integrated, DS3172 Datasheet - Page 113

• Manufacturer Part Number: DS3172
• Description: Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
• Manufacturer: Maxim Integrated

Specifications of DS3172

• Part # Aliases: 90-31720-000

The transmitter line driver can be disabled and the TXPn and TXNn outputs tri-stated by asserting the LTS
configuration bit (PORT.CR2.LTS). Powering down the transmitter through the TPD configuration bit (CPU bus
mode) also tri-states the TXPn and TXNn outputs.
10.12.4.3 Interfacing to the Line
The transmitter interfaces to the outgoing DS3/E3 coaxial cable (75Ω) through a 2:1 step-down transformer
connected to the TXPn and TXNn pins.
recommended interface components.
10.12.4.4 Transmit Driver Monitor
If the transmit driver monitor detects a faulty transmitter, it sets the PORT.SR.TDM status bit. When the transmitter
is tri-stated, the transmit driver monitor is also disabled. The transmitter is declared to be faulty when the
transmitter outputs see a load of less than ~25Ω.
10.12.4.5 Transmitter Power-Down
To minimize power consumption when the transmitter is not being used, assert the PORT.CR1.PD configuration
bit. When the transmitter is powered down, the TXPn and TXNn pins are put in a high-impedance state and the
transmit amplifiers are powered down.
10.12.4.6 Transmitter Jitter Generation (Intrinsic)
The transmitter meets the jitter generation requirements of all applicable standards, with or without the jitter
attenuator enabled.
10.12.4.7 Transmitter Jitter Transfer
Without the jitter attenuator enabled in the transmit side, the transmitter passes jitter through unchanged. With the
jitter attenuator enabled in the transmit side, the transmitter meets the jitter transfer requirements of all applicable
telecommunication standards. See
10.12.5 Receiver
10.12.5.1 Interfacing to the Line
The receiver can be transformer-coupled or capacitor-coupled to the line. Typically, the receiver interfaces to the
incoming coaxial cable (75Ω) through a 1:2 step-up transformer.
transformer and other recommended interface components.
the transformer.
to be in B3ZS- or HDB3-coded AMI format.
Table 10-33. Transformer Characteristics
Turns Ratio
Bandwidth 75Ω
Primary Inductance
Leakage Inductance
Interwinding Capacitance
Isolation Voltage
PARAMETER
Figure 10-32
shows a general overview of the LIU block. The receiver expects the incoming signal
0.250MHz to 500MHz (typ)
Table 4-1.
Table 10-33
1500V
0.12µH (max)
10pF (max)
19µH (min)
1:2ct ±2%
VALUE
Figure 1-1
RMS
(min)
specifies the required characteristics of the transformer.
113
shows the arrangement of the transformer and other
Table 10-33
Figure 1-1
specifies the required characteristics of
shows the arrangement of the