XRT83SL314ES Exar, XRT83SL314ES Datasheet - Page 73

• Manufacturer Part Number: XRT83SL314ES
• Description: LIN Transceivers 14 CHT1/E1 LIUSH
• Manufacturer: Exar

Specifications of XRT83SL314ES

• Product Category: LIN Transceivers
• Rohs: yes

xr
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
CLOCK SELECT REGISTER
The input clock source is used to generate all the necessary clock references internally to the LIU. The
microprocessor timing is derived from a PLL output which is chosen by programming the Clock Select Bits in
register 0xE9h. Therefore, if the clock selection bits are being programmed, the frequency of the PLL output
will be adjusted accordingly. During this adjustment, it is important to "Not" write to any other bit location within
the same register while selecting the input/output clock frequency. For best results, register 0xE9h can be
broken down into two sub-registers with the MSB being bits D[7:4] and the LSB being bits D[3:0] as shown in
Figure 42. Note: Bits D[7:6] are reserved.
F
Programming Examples:
Example 1: Changing bits D[7:4]
If bits D[7:4] are the only values within the register that will change in a WRITE process, the microprocessor
only needs to initiate ONE write operation.
Example 2: Changing bits D[3:0]
If bits D[3:0] are the only values within the register that will change in a WRITE process, the microprocessor
only needs to initiate ONE write operation.
Example 3: Changing bits within the MSB and LSB
In this scenario, one must initiate TWO write operations such that the MSB and LSB do not change within ONE
write cycle. It is recommended that the MSB and LSB be treated as two independent sub-registers. One can
either change the clock selection (LSB) and then change bits D[5:4] (MSB) on the SECOND write, or vice-
versa. No order or sequence is necessary.
IGURE
B
D7
D6
IT
42. R
EGISTER
Reserved
Reserved
N
AME
0
T
X
ABLE
E9
D7
This Register Bit is Not Used
This Register Bit is Not Used
H
ALLT1/E1, CLKCNTL
S
50: M
UB
D6
R
EGISTERS
ICROPROCESSOR
MSB
D5
G
LOBAL
D4
R
F
UNCTION
EGISTER
R
70
EGISTER
D3
(0
X
E9
Clock Selection Bits
0
X
H
E9
D2
)
H
B
IT
LSB
D1
D
ESCRIPTION
D0
Register
Type
R/W
R/W
XRT83SL314
(HW reset)
REV. 1.0.1
Default
Value
0
0