XRT83SL314ES Exar, XRT83SL314ES Datasheet - Page 63

• Manufacturer Part Number: XRT83SL314ES
• Description: LIN Transceivers 14 CHT1/E1 LIUSH
• Manufacturer: Exar

Specifications of XRT83SL314ES

• Product Category: LIN Transceivers
• Rohs: yes

xr
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
B
B
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
IT
IT
Reserved
Reserved
FLSDET
CLOS5
CLOS4
CLOS3
CLOS2
CLOS1
CLOS0
1SEG6
1SEG5
1SEG4
1SEG3
1SEG2
1SEG1
1SEG0
N
N
AME
AME
T
T
ABLE
ABLE
This Register Bit is Not Used.
FIFO LIMIT STATUS DETECT
The FLSDET is used to determine whether the receiver or trans-
mitter FIFO has reached its limit status. If both FIFOs reach their
limit capacity, this bit will be set to "1".
0 = Receive JA
1 = Transmit JA
Cable Loss Indication
This 6-Bit binary word indicates the cable attenuation on the
receiver inputs RTIP/RRING within ±1dB with Bit 5 being the MSB.
This Register Bit is Not Used
Arbitrary Pulse Generation
The transmit output pulse is divided into 8 individual segments.
This register is used to program the first segment which corre-
sponds to the overshoot of the pulse amplitude. There are four
segments for the top portion of the pulse and four segments for the
bottom portion of the pulse. Segment number 5 corresponds to
the undershoot of the pulse. The MSB of each segment is the sign
bit.
Bit 6 = 0 = Negative Direction
Bit 6 = 1 = Positive Direction
32: M
33: M
ICROPROCESSOR
ICROPROCESSOR
C
C
HANNEL
HANNEL
0-13 (0
0-13 (0
F
F
UNCTION
UNCTION
R
R
60
EGISTER
EGISTER
X
X
07
08
H
H
-0
-0
0
X
0
X
D7
D8
X
X
07
08
H
H
)
)
H
H
B
B
IT
IT
D
D
ESCRIPTION
ESCRIPTION
Register
Register
Type
Type
R/W
RO
RO
X
XRT83SL314
(HW reset)
(HW reset)
REV. 1.0.1
Default
Default
Value
Value
0
0
0
0
0
0
0
0
0
0