XRT83SL314ES Exar, XRT83SL314ES Datasheet - Page 57

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XRT83SL314ES

Manufacturer Part Number
XRT83SL314ES
Description
LIN Transceivers 14 CHT1/E1 LIUSH
Manufacturer
Exar
Datasheet

Specifications of XRT83SL314ES

Product Category
LIN Transceivers
Rohs
yes
xr
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
B
B
D1
D0
D7
D6
D5
D4
IT
IT
INVQRSS
TxTEST2
TxTEST1
TxTEST0
FIFOS
JABW
N
N
AME
AME
T
T
ABLE
ABLE
Jitter Bandwidth (E1 Mode Only, T1 is permanently set to 3Hz)
The jitter bandwidth is a global setting that is applied to both the
receiver and transmitter jitter attenuator.
0 = 10Hz
1 = 1.5Hz
FIFO Depth Select
The FIFO depth select is used to configure the part for a 32-bit or
64-bit FIFO (within the jitter attenuator blocks). The delay of the
FIFO is equal to ½ the FIFO depth. This is a global setting that is
applied to both the receiver and transmitter FIFO.
0 = 32-Bit
1 = 64-Bit
QRSS inversion
INVQRSS is used to invert the transmit QRSS pattern set by the
TxTEST[2:0] bits. By default, INVQRSS is disabled and the QRSS
will be transmitted with normal polarity.
0 = Disabled
1 = Enabled
Test Code Pattern
TxTEST[2:0] are used to select a diagnostic test pattern to the line
(transmit outputs).
0XX = No Pattern
100 = Tx QRSS
101 = Tx TAOS
110 = Tx TLUC
111 = Tx TLDC
26: M
27: M
ICROPROCESSOR
ICROPROCESSOR
C
C
HANNEL
HANNEL
0-13 (0
0-13 (0
F
F
UNCTION
UNCTION
R
R
54
EGISTER
EGISTER
X
X
01
02
H
H
-0
-0
0
X
0
X
D1
D2
X
X
01
02
H
H
)
)
H
H
B
B
IT
IT
D
D
ESCRIPTION
ESCRIPTION
Register
Register
Type
Type
R/W
R/W
R/W
R/W
XRT83SL314
(HW reset)
(HW reset)
REV. 1.0.1
Default
Default
Value
Value
0
0
0
0
0
0

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