XRT83SL314ES Exar, XRT83SL314ES Datasheet - Page 68

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XRT83SL314ES

Manufacturer Part Number
XRT83SL314ES
Description
LIN Transceivers 14 CHT1/E1 LIUSH
Manufacturer
Exar
Datasheet

Specifications of XRT83SL314ES

Product Category
LIN Transceivers
Rohs
yes
XRT83SL314
REV. 1.0.1
B
B
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
IT
IT
EQFLAG5
EQFLAG4
EQFLAG3
EQFLAG2
EQFLAG1
EQFLAG0
RxTCNTL
Reserved
Reserved
Reserved
Reserved
EQG1
EQG0
N
N
SL1
SL0
AME
AME
T
ABLE
Receive Termination Select Control
This bit sets the LIU to control the RxTSEL function with either the
individual channel register bit or the global hardware pin.
0 = Control of the receive termination is set to the register bits
1 = Control of the receive termination is set to the hardware pin
Equalizer Attenuation Flag
EQFLAG[5:0] is used to generate an interrupt condition for an
RLOS other than the default setting described in the datasheet. A
desired value can be programmed into this register. If EQFLAGE
is enabled in register 0x04h and if this 6-Bit binary word is equal to
the 6-Bit cable loss indicator, an interrupt will be generated.
This Register Bit is Not Used
This Register Bit is Not Used
This Register Bit is Not Used
This Register Bit is Not Used
Slicer Level Select
00 = 50%
01 = 45%
10 = 55%
11 = 68%
Equalizer Gain Control
00 = Normal
01 = Reduce Gain by 1dB
10 = Reduce Gain by 3dB
11 = Normal
44: M
ICROPROCESSOR
G
G
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
LOBAL
LOBAL
R
F
R
F
UNCTION
UNCTION
EGISTER
EGISTER
R
65
EGISTER
(0
(0
X
X
E2
E3
0
X
H
H
E3
)
)
H
B
IT
D
ESCRIPTION
Register
Register
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
xr
(HW reset)
(HW reset)
Default
Default
Value
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0

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