XRT83SL314ES Exar, XRT83SL314ES Datasheet - Page 4

• Manufacturer Part Number: XRT83SL314ES
• Description: LIN Transceivers 14 CHT1/E1 LIUSH
• Manufacturer: Exar

Specifications of XRT83SL314ES

• Product Category: LIN Transceivers
• Rohs: yes

XRT83SL314
REV. 1.0.1
GENERAL DESCRIPTION.............................................................................................................. 1
T
PIN DESCRIPTIONS BY FUNCTION ............................................................................................. 4
1.0 CLOCK SYNTHESIZER .......................................................................................................................14
2.0 RECEIVE PATH LINE INTERFACE .....................................................................................................15
ABLE OF
F
T
F
F
T
F
T
F
F
F
F
T
F
F
T
F
F
F
F
T
F
F
F
IGURE
ABLE
IGURE
IGURE
ABLE
IGURE
ABLE
IGURE
IGURE
IGURE
IGURE
ABLE
IGURE
IGURE
ABLE
IGURE
IGURE
IGURE
IGURE
ABLE
IGURE
IGURE
IGURE
APPLICATIONS .......................................................................................................................................................... 1
FEATURES
PRODUCT ORDERING INFORMATION ..................................................................................................2
P
M
R
T
C
C
P
N
1.1 ALL T1/E1 MODE ........................................................................................................................................... 15
2.1 LINE TERMINATION (RTIP/RRING) .............................................................................................................. 16
2.2 EQUALIZER CONTROL ................................................................................................................................. 18
2.3 CABLE LOSS INDICATOR ............................................................................................................................. 18
2.4 EQUALIZER ATTENUATION FLAG .............................................................................................................. 19
2.5 PEAK DETECTOR AND SLICER ................................................................................................................... 19
2.6 CLOCK AND DATA RECOVERY ................................................................................................................... 20
2.7 RECEIVE JITTER ATTENUATOR .................................................................................................................. 25
2.8 HDB3/B8ZS DECODER .................................................................................................................................. 25
2.9 RPOS/RNEG/RCLK ........................................................................................................................................ 26
RANSMITTER
IN
OWER AND
ECEIVER
ONTROL
LOCK
O
ICROPROCESSOR
C
O
1: I
2: S
3: S
4: S
5: T
6: A
2.1.1 CASE 1: INTERNAL TERMINATION.......................................................................................................................... 16
2.1.2 CASE 2: INTERNAL TERMINATION WITH ONE EXTERNAL FIXED RESISTOR FOR ALL MODES..................... 17
2.6.1 RECEIVE SENSITIVITY .............................................................................................................................................. 21
2.6.2 INTERFERENCE MARGIN ......................................................................................................................................... 22
2.6.3 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ........................................................................ 22
1. B
2. S
3. S
4. T
5. T
6. S
7. S
8. S
9. R
10. R
11. T
12. T
13. I
14. A
15. P
16. S
17. D
ONNECTS
UT OF THE
S
NPUT
ELECTING THE
ELECTING THE
ELECTING THE
IMING
NALOG
ECTION
C
YPICAL
2.6.3.1 RLOS (R
2.6.3.2 EXLOS (E
2.6.3.3 AIS (A
2.6.3.4 NLCD (N
2.6.3.5 FLSD (FIFO L
2.6.3.6 LCVD (L
LOCK
IMPLIFIED
IMPLIFIED
IMPLIFIED
ECEIVE
NTERRUPT
YPICAL
F
IMPLIFIED
IMPLIFIED
..................................................................................................................................................................... 2
S
EST
EST
NALOG
ROCESS
INGLE
ECEIVE
UAL
ONTENTS
UNCTION
ECTION
G
C
S
S
LOCK
ROUND
C
C
D
R
RLOS D
............................................................................................................................................................ 13
PECIFICATIONS FOR
ECTION
C
ONFIGURATION FOR
ONFIGURATION FOR
IAGRAM OF THE
AIL
.......................................................................................................................................................... 10
D
R
C
XRT83SL314 ..................................................................................................................................... 3
R
ONNECTION
D
AIL
ATA
ONNECTION
B
B
B
B
ECEIVE
B
B
........................................................................................................................................................ 4
ATA
M
S
G
....................................................................................................................................................... 5
LOCK
LOCK
LOCK
LOCK FOR
.................................................................................................................................................... 10
LOCK
LOCK
OURCE
M
ODE
ENERATION
I
V
S
.................................................................................................................................................. 11
U
NTERNAL
LARM
ALUE OF THE
LICER
ECLARE
ODE
U
.................................................................................................................................................. 8
PDATED ON THE
PDATED ON THE
INE
............................................................................................................
D
D
D
ECEIVER
ETWORK
W
D
D
L
XTENDED
IAGRAM OF THE
IAGRAM OF THE
IAGRAM OF THE
OS OF
W
IAGRAM OF THE
IAGRAM OF THE
ITH A
S
C
D
I
L
NDICATION
D
ELECT
ITH A
A
/C
IAGRAM
EVEL FOR THE
ODE
IMIT
XRT83SL314.................................................................................................................................. 1
IAGRAM
I
UTOMATIC
MPEDANCE
P
LEAR
F
S
RCLK/RPOS/RNEG................................................................................................................. 21
L
ROCESS
L
M
M
IXED
S
V
IGNAL FOR
F
OSS OF
OOP
.............................................................................................................................................. 14
E
L
TATUS
IOLATION
IXED
EASURING
EASURING
XTERNAL
OSS OF
(T
U
U
R
R
SING
YPICAL
S
C
F
SING
TABLE OF CONTENTS
ISING
EPEATING
L
R
IGNAL
ALLING
ODE
E
C
E
.................................................................................................................................... 16
B
C
R
OOP
EPEATING
S
D
QUALIZER AND
QUALIZER
ABLE
LOCK
P
LOCK
ECEIVE
IGNAL
ETECTION
O
S
I
T1/E1/J1................................................................................................................ 23
D
EAK
NTERNAL
F
E
D
IGNAL
NE
R
I
NTERFERENCE
V
) ......................................................................................................................... 23
C
ETECTION
IXED
DGE OF
ETECTION
ECEIVE
ALUES
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
E
ODE
L
......................................................................................................................... 22
E
S
D
) ..................................................................................................................... 22
OSS
DGE OF
"0011" P
XTERNAL
YNTHESIZER
P
ETECTOR
) .................................................................................................................. 23
R
"0011" P
ATH
A
D
) ............................................................................................................... 25
ESISTOR
)
I
TTENUATION
ETECTION
T
NDICATOR
RCLK..................................................................................................... 20
S
FOR
) ........................................................................................................... 25
ERMINATION
ENSITIVITY
) .......................................................................................................... 24
............................................................................................................ 15
P
RCLK................................................................................................. 20
EAK
ATTERN
F
....................................................................................................... 19
T1/E1 ............................................................................................. 23
M
ATTERN
IXED
I
.................................................................................................... 17
................................................................................................... 15
ARGIN
D
................................................................................................ 18
................................................................................................ 24
ETECTOR
R
F
............................................................................................ 21
............................................................................................ 26
ESISTOR
LAG
.......................................................................................... 16
......................................................................................... 22
......................................................................................... 26
.................................................................................... 19
................................................................................. 18
.............................................................................. 17
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