XRT83SL314ES Exar, XRT83SL314ES Datasheet - Page 23

• Manufacturer Part Number: XRT83SL314ES
• Description: LIN Transceivers 14 CHT1/E1 LIUSH
• Manufacturer: Exar

Specifications of XRT83SL314ES

• Product Category: LIN Transceivers
• Rohs: yes

xr
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
The receive clock (RCLK) is recovered by the clock and data recovery circuitry. An internal PLL locks on the
incoming data stream and outputs a clock that’s in phase with the incoming signal. This allows for multi-
channel T1/E1/J1 signals to arrive from different timing sources and remain independent. In the absence of an
incoming signal, RCLK maintains its timing by using the internal master clock as its reference. The recovered
data can be updated on either edge of RCLK. By default, data is updated on the rising edge of RCLK. To
update data on the falling edge of RCLK, set RCLKE to "1" in the appropriate global register. Figure 9 is a
timing diagram of the receive data updated on the rising edge of RCLK. Figure 10 is a timing diagram of the
receive data updated on the falling edge of RCLK. The timing specifications are shown in Table 5.
F
F
2.6
IGURE
IGURE
9. R
10. R
Clock and Data Recovery
ECEIVE
ECEIVE
D
D
ATA
ATA
R P O S
R N E G
R C LK
or
U
RPOS
RNEG
RCLK
U
PDATED ON THE
or
PDATED ON THE
R
R
F
ISING
D Y
R
ALLING
DY
E
DGE OF
E
20
DGE OF
R
R
RCLK
O H
OH
R C LK
RCLK
RCLK
F
R
RCLK
R C L K
R
F
XRT83SL314
REV. 1.0.1