S912XEQ512J3CAGR Freescale Semiconductor, S912XEQ512J3CAGR Datasheet - Page 677

• Manufacturer Part Number: S912XEQ512J3CAGR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XEQ512J3CAGR

• Rohs: yes
• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 kB
• Data Ram Size: 32 kB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• Interface Type: CAN/SCI/SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 18
Periodic Interrupt Timer (S12PIT24B4CV2)
18.1
The period interrupt timer (PIT) is an array of 24-bit timers that can be used to trigger peripheral modules
or raise periodic interrupts. Refer to
18.1.1
18.1.2
The PIT includes these features:
18.1.3
Refer to the device overview for a detailed explanation of the chip modes.
Freescale Semiconductor
Revision
Number
V01.00
V01.01
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•
•
•
•
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micro time bases
Four timers implemented as modulus down-counters with independent time-out periods.
Time-out periods selectable between 1 and 2
cycles with 1 <= m <= 256 and 1 <= n <= 65536.
Timers that can be enabled individually.
Four time-out interrupts.
Four time-out trigger output signals available to trigger peripheral modules.
Start of timer channels can be aligned to each other.
Introduction
Glossary
Features
Modes of Operation
CCR
SoC
28 Apr 2005
ISR
05 Jul 2005
PIT
Revision
Date
18.6/18-690
Sections
Affected
Periodic Interrupt Timer
Interrupt Service Routine
Condition Code Register
System on Chip
clock periods of the 16-bit timer modulus down-counters, which are generated by the 8-bit
modulus down-counters.
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 18-1
Table 18-1. Revision History
Acronyms and Abbreviations
- Initial Release
- Added application section.
- Removed table 1-1
for a simplified block diagram.
24
bus clock cycles. Time-out equals m*n bus clock
Description of Changes
677