S912XEQ512J3CAGR Freescale Semiconductor, S912XEQ512J3CAGR Datasheet - Page 515

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S912XEQ512J3CAGR

Manufacturer Part Number
S912XEQ512J3CAGR
Description
16-bit Microcontrollers - MCU 16 BIT,512K FLASH
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S912XEQ512J3CAGR

Rohs
yes
Core
HCS12X
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 kB
Data Ram Size
32 kB
On-chip Adc
Yes
Package / Case
LQFP
Mounting Style
SMD/SMT
Interface Type
CAN/SCI/SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
119
Number Of Timers
25
Program Memory Type
Flash
Supply Voltage - Max
1.98 V, 2.9 V, 5.5 V
Supply Voltage - Min
1.72 V, 2.7 V, 3.13 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S912XEQ512J3CAGR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
13.3.2.6
Writes to this register will abort current conversion sequence and start a new conversion sequence. If
external trigger is enabled (ETRIGE=1) an initial write to ATDCTL5 is required to allow starting of a
conversion sequence which will then occur on each trigger event. Start of conversion means the beginning
of the sampling phase.
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0005
SMP[2:0]
PRS[4:0]
Reset
Field
7–5
4–0
W
R
Sample Time Select — These three bits select the length of the sample time in units of ATD conversion clock
cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4-0).
Table 13-14
ATD Clock Prescaler — These 5 bits are the binary prescaler value PRS. The ATD conversion clock frequency
is calculated as follows:
Refer to Device Specification for allowed frequency range of f
ATD Control Register 5 (ATDCTL5)
0
0
7
lists the available sample time lengths.
f ATDCLK
SMP2
SC
0
6
0
0
0
0
1
1
1
1
Figure 13-8. ATD Control Register 5 (ATDCTL5)
MC9S12XE-Family Reference Manual Rev. 1.25
Table 13-13. ATDCTL4 Field Descriptions
=
------------------------------------ -
2
SMP1
SCAN
×
Table 13-14. Sample Time Select
(
0
0
1
1
0
0
1
1
0
f BUS
5
PRS
+
1
)
SMP0
MULT
0
1
0
1
0
1
0
1
0
4
Description
ATD Clock Cycles
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)
CD
0
3
Sample Time
in Number of
ATDCLK
10
12
16
20
24
4
6
8
.
CC
0
2
CB
0
1
CA
0
0
515

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