S912XEQ512J3CAGR Freescale Semiconductor, S912XEQ512J3CAGR Datasheet - Page 488

• Manufacturer Part Number: S912XEQ512J3CAGR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XEQ512J3CAGR

• Rohs: yes
• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 kB
• Data Ram Size: 32 kB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• Interface Type: CAN/SCI/SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
11.4.1.2
The clock generator creates the clocks used in the MCU (see
on top of the individual clock gates indicates the dependencies of different modes (STOP, WAIT) and the
setting of the respective configuration bits.
The peripheral modules use the Bus Clock. Some peripheral modules also use the Oscillator Clock. If the
MCU enters Self Clock Mode (see
switched to PLLCLK running at its minimum frequency f
visible at the ECLK pin. The Core Clock signal is the clock for the CPU. The Core Clock is twice the Bus
Clock. But note that a CPU cycle corresponds to one Bus Clock.
IPLL clock mode is selected with PLLSEL bit in the CLKSEL register. When selected, the IPLL output
clock drives SYSCLK for the main system including the CPU and peripherals. The IPLL cannot be turned
off by clearing the PLLON bit, if the IPLL clock is selected. When PLLSEL is changed, it takes a
maximum of 4 OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks
freeze and CPU activity ceases.
488
EXTAL
XTAL
Condition
OSCILLATOR
Gating
System Clocks Generator
LOOP (IIPLL)
= Clock Gate
PHASE
LOCK
OSCCLK
PLLCLK
Monitor
Clock
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 11-16. System Clocks Generator
Section 11.4.2.2, “Self Clock
PLLSEL or SCM
1
0
1
0
SCM
STOP(PSTP, PCE),
STOP(PSTP, PRE),
WAIT(COPWAI),
WAIT(RTIWAI),
COP ENABLE
RTI ENABLE
SYSCLK
STOP
SCM
. The Bus Clock is used to generate the clock
Figure
STOP
Mode”) Oscillator clock source is
11-16). The gating condition placed
÷2
CLOCK PHASE
GENERATOR
COP
RTI
Freescale Semiconductor
Core Clock
Bus Clock
Oscillator
Clock