S912XEQ512J3CAGR Freescale Semiconductor, S912XEQ512J3CAGR Datasheet - Page 404
S912XEQ512J3CAGR
Manufacturer Part Number
S912XEQ512J3CAGR
Description
16-bit Microcontrollers - MCU 16 BIT,512K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEQ512J3CAGR.pdf
(1324 pages)
Specifications of S912XEQ512J3CAGR
Rohs
yes
Core
HCS12X
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 kB
Data Ram Size
32 kB
On-chip Adc
Yes
Package / Case
LQFP
Mounting Style
SMD/SMT
Interface Type
CAN/SCI/SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
119
Number Of Timers
25
Program Memory Type
Flash
Supply Voltage - Max
1.98 V, 2.9 V, 5.5 V
Supply Voltage - Min
1.72 V, 2.7 V, 3.13 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S912XEQ512J3CAGR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 404 of 1324
- Download datasheet (5Mb)
BFINSX
Chapter 10 XGATE (S12XGATEV3)
Operation
!(RS1[w:0] ^ RD[w+o:o]) ⇒ RD[w+o:o];
Extracts w+1 bits from register RS1 starting at position 0, performs an XNOR with RD[w+o:o] and writes
the bits back to RD. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored.
Using R0 as a RS1, this command can be used to toggle bits.
CCR Effects
Code and CPU Cycles
404
N:
Z:
V:
C:
BFINSX RD, RS1, RS2
N
∆
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
0; cleared.
Not affected.
Z
∆
w = (RS2[7:4])
o = (RS2[3:0])
V
0
Source Form
—
C
15
15
15
MC9S12XE-Family Reference Manual Rev. 1.25
Address
Mode
Bit Field Insert and XNOR
TRI
7
0
1
W4
1
5
W4=3, O4=2
1
4
1
3
3
Machine Code
RD
2
O4
Bit Field Insert XNOR
0
0
0
RS1
RS2
RS1
RD
BFINSX
RS2
Freescale Semiconductor
1
1
Cycles
P
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