S912XEQ512J3CAGR Freescale Semiconductor, S912XEQ512J3CAGR Datasheet - Page 167

• Manufacturer Part Number: S912XEQ512J3CAGR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XEQ512J3CAGR

• Rohs: yes
• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 kB
• Data Ram Size: 32 kB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• Interface Type: CAN/SCI/SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

1. Read: Always reads 0x00
1. Read: Anytime.
2.3.91
2.3.92
Freescale Semiconductor
Address 0x036E
Address 0x036F
PTRRR
PTRRR
Write: Unimplemented
Write: Anytime.
PPSR
Field
Field
Reset
Reset
7-0
7
6
W
W
R
R
Port R pull device select—Determine pull device polarity on input pins
This register selects whether a pull-down or a pull-up device is connected to the pin.
1 A pull-down device is connected to the associated pin, if enabled and if the pin is used as input.
0 A pull-up device is connected to the associated pin, if enabled and if the pin is used as input.
PTRRR7
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC7 is available on PP7
0 TIMIOC7 is available on PR7
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC6 is available on PP6
0 TIMIOC6 is available on PR6
PIM Reserved Register
Port R Routing Register (PTRRR)
0
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
PTRRR6
0
0
0
6
6
Table 2-87. PTR Routing Register Field Descriptions
Figure 2-90. Port R Routing Register (PTRRR)
Table 2-86. PPSR Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
PTRRR5
Figure 2-89. PIM Reserved Register
0
0
0
5
5
PTRRR4
0
0
0
4
4
Description
Description
PTRRR3
3
0
0
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
PTRRR2
0
0
0
2
2
Access: User read/write
PTRRR1
0
0
0
1
1
Access: User read
PTRRR0
0
0
0
0
0
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