S912XEQ512J3CAGR Freescale Semiconductor, S912XEQ512J3CAGR Datasheet - Page 156

• Manufacturer Part Number: S912XEQ512J3CAGR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XEQ512J3CAGR

• Rohs: yes
• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 kB
• Data Ram Size: 32 kB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• Interface Type: CAN/SCI/SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

1. Read: Anytime.
1. Read: Anytime.
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.71
2.3.72
156
DDR0AD0
Address 0x0272
Address 0x0273
Write: Anytime.
Write: Anytime.
Field
Reset
Reset
7-0
W
W
R
R
DDR0AD07
DDR1AD07
Port AD0 data direction—
This register controls the data direction of pins 15 through 8.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port AD0 Data Direction Register 0 (DDR0AD0)
Port AD0 Data Direction Register 1 (DDR1AD0)
0
0
7
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PT0AD0 registers, when changing the
DDR0AD0 register.
To use the digital input function on Port AD0 the ATD Digital Input Enable
Register (ATD0DIEN1) has to be set to logic level “1”.
DDR0AD06
DDR1AD06
Figure 2-69. Port AD0 Data Direction Register 0 (DDR0AD0)
Figure 2-70. Port AD0 Data Direction Register 1 (DDR1AD0)
0
0
6
6
Table 2-67. DDR0AD0 Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
DDR0AD05
DDR1AD05
0
0
5
5
DDR0AD04
DDR1AD04
NOTE
NOTE
0
0
4
4
Description
DDR0AD03
DDR1AD03
3
0
3
0
DDR0AD02
DDR1AD02
0
0
2
2
DDR0AD01
DDR1AD01
Access: User read/write
Access: User read/write
Freescale Semiconductor
0
0
1
1
DDR0AD00
DDR1AD00
0
0
0
0
(1)
(1)