S912XEQ512J3CAGR Freescale Semiconductor, S912XEQ512J3CAGR Datasheet - Page 605

• Manufacturer Part Number: S912XEQ512J3CAGR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XEQ512J3CAGR

• Rohs: yes
• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 kB
• Data Ram Size: 32 kB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• Interface Type: CAN/SCI/SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 16
Freescale’s Scalable Controller Area Network
(S12MSCANV3)
16.1
Freescale’s scalable controller area network (S12MSCANV3) definition is based on the MSCAN12
definition, which is the specific implementation of the MSCAN concept targeted for the S12, S12X and
S12Z microcontroller families.
The module is a communication controller implementing the CAN 2.0A/B protocol as defined in the
Bosch specification dated September 1991. For users to fully understand the MSCAN specification, it is
recommended that the Bosch specification be read first to familiarize the reader with the terms and
concepts contained within this document.
Though not exclusively intended for automotive applications, CAN protocol is designed to meet the
specific requirements of a vehicle serial data bus: real-time processing, reliable operation in the EMI
environment of a vehicle, cost-effectiveness, and required bandwidth.
MSCAN uses an advanced buffer arrangement resulting in predictable real-time behavior and simplified
application software.
Freescale Semiconductor
Revision
Number
V03.13
V03.14
V03.15
Introduction
Revision Date
12 Nov 2012
03 Mar 2011
12 Jan 2013
16.3.2.15/16-
Figure 16-37
16.1/16-605
Table 16-11
Table 16-26
Figure 16-4
Table 16-3
Table 16-3
Sections
Affected
626
MC9S12XE-Family Reference Manual Rev. 1.25
Table 16-1. Revision History
• Corrected CANE write restrictions
• Removed footnote from RXFRM bit
• Corrected RxWRN and TxWRN threshold values
• Updated TIME bit description
• Added register names to buffer map
• Updated TSRH and TSRL read conditions
• Updated introduction
• Updated CANTXERR and CANRXERR register notes
Description of Changes
605