S912XEQ512J3CAGR Freescale Semiconductor, S912XEQ512J3CAGR Datasheet - Page 176
S912XEQ512J3CAGR
Manufacturer Part Number
S912XEQ512J3CAGR
Description
16-bit Microcontrollers - MCU 16 BIT,512K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEQ512J3CAGR.pdf
(1324 pages)
Specifications of S912XEQ512J3CAGR
Rohs
yes
Core
HCS12X
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 kB
Data Ram Size
32 kB
On-chip Adc
Yes
Package / Case
LQFP
Mounting Style
SMD/SMT
Interface Type
CAN/SCI/SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
119
Number Of Timers
25
Program Memory Type
Flash
Supply Voltage - Max
1.98 V, 2.9 V, 5.5 V
Supply Voltage - Min
1.72 V, 2.7 V, 3.13 V
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
S912XEQ512J3CAGR
Manufacturer:
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Quantity:
10 000
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1. Read: Anytime.
1. Read: Anytime.
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.104 Port F Reduced Drive Register (RDRF)
2.3.105 Port F Pull Device Enable Register (PERF)
176
Address 0x037B
Address 0x037C
Write: Anytime.
Write: Anytime.
RDRF
PERF
Field
Field
Reset
Reset
7-0
7-0
W
W
R
R
Port F reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced independent of the
function used on the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
Port F pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset all pull devices are enabled.
1 Pull device enabled.
0 Pull device disabled.
RDRF7
PERF7
0
1
7
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTF or PTIF registers, when changing the
DDRF register.
RDRF6
PERF6
Figure 2-103. Port F Pull Device Enable Register (PERF)
0
1
6
6
Figure 2-102. Port F Reduced Drive Register (RDRF)
Table 2-100. PERF Register Field Descriptions
Table 2-99. RDRF Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
RDRF5
PERF5
0
1
5
5
RDRF4
PERF4
NOTE
0
1
4
4
Description
Description
RDRF3
PERF3
3
0
3
1
RDRF2
PERF2
0
1
2
2
Access: User read/write
Access: User read/write
Freescale Semiconductor
RDRF1
PERF1
0
1
1
1
RDRF0
PERF0
0
1
0
0
(1)
(1)
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