MC56F8035VLD Freescale Semiconductor, MC56F8035VLD Datasheet - Page 93

• Manufacturer Part Number: MC56F8035VLD
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLD

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

6.3.12
See
6.3.12.1
This bit field is reserved. It must be set to 0.
6.3.12.2
6.3.12.3
6.3.12.4
6.3.12.5
This bit field is reserved. Each bit must be set to 0.
6.3.12.6
6.3.12.7
Freescale Semiconductor
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Section 6.3.11
RESET
Write
Read
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
Stop Disable Register 1 (SD1)
Reserved—Bit 15
Programmable Interval Timer 2 Clock Stop Disable (PIT2_SD)—Bit 14
Programmable Interval Timer 1 Clock Stop Disable (PIT1_SD)—Bit 13
Programmable Interval Timer 0 Clock Stop Disable (PIT0_SD)—Bit 12
Reserved—Bits 11–4
Quad Timer A, Channel 3 Clock Stop Disable (TA3_SD)—Bit 3
Quad Timer A, Channel 2 Clock Stop Disable (TA2_SD)—Bit 2
15
0
0
for general information about Stop Disable Registers.
PIT2_
14
SD
0
PIT1_
13
SD
0
Figure 6-13 Stop Disable Register 1 (SD1)
PIT0_
SD
12
0
56F8035/56F8025 Data Sheet, Rev. 6
11
0
0
10
0
0
9
0
0
8
0
0
7
0
0
6
0
0
5
0
0
4
0
0
TA3_
SD
3
0
TA2_
SD
Register Descriptions
2
0
TA1_
SD
1
0
TA0_
SD
0
0
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