MC56F8035VLD Freescale Semiconductor, MC56F8035VLD Datasheet - Page 110

• Manufacturer Part Number: MC56F8035VLD
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLD

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

POR resets are extended 64 OSC_CLK clocks to stabilize the power supply and clock source. All resets
are subsequently extended for an additional 32 OSC_CLK clocks and 64 system clocks as the various
internal reset controls are released. Given the normal relaxation oscillator rate of 8MHz, the duration of a
POR reset from when power comes on to when code is running is 28µS. An external reset generation
circuit may also be used. A description of how these resets are used to initialize the clocking system and
system modules is included in
6.7 Clocks
The memory, peripheral and core clocks all operate at the same frequency (32MHz maximum), with the
exception of the peripheral clocks for quad timers TMRA and TMRB and the PWM, which have the option
to operate at 3X system clock. The SIM is responsible for clock distributions.
While the SIM generates the ADC peripheral clock in the same way it generates all other peripheral clocks,
the ADC standby and conversion clocks are generated by a direct interface between the ADC and the
OCCS module.
110
(active low)
(active low)
(active low)
(active low)
COP_TOR
COP_LOR
RESET IN
Power-On
External
Reset
Figure 6-28 Sources of RESET Functional Diagram (Test modes not included)
RESET
POR
Delay blocks assert immediately and
deassert only after the programmed
number of clock cycles.
pulse shaper
OSC_CLK
Delay 64
Clock
SW Reset
Section
COMBINED_RST
pulse shaper
OSC_CLK
Delay 32
Clock
56F8035/56F8025 Data Sheet, Rev. 6
6.7.
EXTENDED_POR
pulse shaper
CLKGEN_RST
sys clocks
Delay 32
pulse shaper
sys clocks
Delay 32
OCCS
PERIP_RST
CORE_RST
Freescale Semiconductor
Peripherals
Subsystem
Memory
JTAG
56800E