MC56F8035VLD Freescale Semiconductor, MC56F8035VLD Datasheet - Page 87

• Manufacturer Part Number: MC56F8035VLD
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLD

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

6.3.7.1
This bit field is reserved. Each bit must be set to 0.
6.3.7.2
6.3.7.3
6.3.7.4
6.3.7.5
6.3.7.6
This bit field is reserved for factory test. It must be set to 1.
6.3.7.7
This bit field is reserved for factory test. Each bit must be set to 0.
6.3.8
By default, all peripherals are clocked at the system clock rate, which has a maximum of 32MHz. Selected
peripherals clocks have the option to be clocked at 3X system clock rate, which has a maximum of 96MHz,
if the PLL output clock is selected as the system clock. If PLL is disabled, the 3X system clock will not be
available. This register is used to enable high-speed clocking for those peripherals that support it.
Note:
6.3.8.1
This bit field is reserved. Each bit must be set to 0.
Freescale Semiconductor
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Base + $B
RESET
Read
Write
0 = Peripheral output function of GPIOA[3] is defined to be PWM3
1 = Peripheral output function of GPIOA[3] is defined to be the Relaxation Oscillator Clock
0 = Peripheral output function of GPIOA[2] is defined to be PWM2
1 = Peripheral output function of GPIOA[2] is defined to be the system clock
0 = Peripheral output function of GPIOA[1] is defined to be PWM1
1 = Peripheral output function of GPIOA[1] is defined to be 2X system clock
0 = Peripheral output function of GPIOA[0] is defined to be PWM0
1 = Peripheral output function of GPIOA[0] is defined to be 3X system clock
Peripheral Clock Rate Register (SIM_PCR)
Operation is unpredictable if peripheral clocks are reconfigured at runtime, so peripherals should be
disabled before a peripheral clock is reconfigured.
Reserved—Bits 15–10
PWM3—Bit 9
PWM2—Bit 8
PWM1—Bit 7
PWM0—Bit 6
Reserved—Bit 5
Reserved—Bits 4–0
Reserved—Bits 15
15
0
0
Figure 6-9 Peripheral Clock Rate Register (SIM_PCR)
TMRA_
CR
14
0
PWM_
CR
13
0
I2C_
CR
12
0
56F8035/56F8025 Data Sheet, Rev. 6
11
0
0
10
0
0
9
0
0
8
0
0
7
0
0
6
0
0
5
0
0
4
0
0
3
0
0
Register Descriptions
2
0
0
1
0
0
0
0
0
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