MC56F8035VLD Freescale Semiconductor, MC56F8035VLD Datasheet
MC56F8035VLD
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MC56F8035VLD Summary of contents
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Data Sheet Technical Data 56F8000 16-bit Digital Signal Controllers MC56F8025 Rev. 6 02/2010 freescale.com ...
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... Typical: was 190 A, is 440 A Maximum: was 250 A, is 550 A Table 10-12 (was “Output frequency after application of 8MHz trim Figure 10-5. 2-3, change V value from 4 2.2 F. CAP Section 7, Security Features. 56F8035/56F8025 Data Sheet, Rev. 6 Section 5.6.8. Table 10-6 as follows: as follows: Table 10-20 (was +/- 20 mV, is ±35 mV). Freescale Semiconductor ...
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... Added MC56F8035 device Added MC56F8025MLD to the orderable parts In the System Integration Module (SIM) chapter, fixed typos Added IPS0_PSRC2 field to SIM_IPS0 register Please see http://www.freescale.com for the most current data sheet revision. Freescale Semiconductor Document Revision History Description of Change 56F8035/56F8025 Data Sheet, Rev ...
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... Supervisor Data ALU Bit -> 36-Bit MAC Manipulation Three 16-bit Input Registers Unit Four 36-bit Accumulators R/W Control System Bus Control XTAL, CLKIN System O O Integration Clock R S Module Generator* C EXTAL or GPIOD *Includes On-Chip Relaxation Oscillator Freescale Semiconductor GPIOD ...
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... Resets 109 6.7 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.8 Interrupts 112 Part 7 Security Features 112 7.1 Operation with Security Enabled 112 7.2 Flash Access Lock and Unlock Mechanisms . . . . . . . . . . . . . . . . . 113 Freescale Semiconductor 7.3 Product Analysis 114 Part 8 General-Purpose Input/Output (GPIO .114 8.1 Introduction 114 8.2 Configuration . . . . . . . . . . . . . . . . . . . . 114 8.3 Reset Values . . . . . . . . . . . . . . . . . . . . 117 Part 9 Joint Test Action Group (JTAG .122 9 ...
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... Program Flash (56F8025 device) — 8KB of Unified Data/Program RAM (56F8035 device) 4KB of Unified Data/Program RAM (56F8025 device) • EEPROM emulation capability using Flash 6 Table 1-1 Device Differences On-Chip Memory 56F8035 56F8025 64KB 8KB 56F8035/56F8025 Data Sheet, Rev. 6 32KB 4KB Freescale Semiconductor ...
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... One Queued Serial Communication Interface (QSCI) with LIN Slave functionality — Full-duplex or single-wire operation — Two receiver wake-up methods: – Idle line – Address mark — Four-bytes-deep FIFOs are available on both transmitter and receiver • One Queued Serial Peripheral Interfaces (QSPI) Freescale Semiconductor 56F8035/56F8025 Data Sheet, Rev. 6 56F8035/56F8025 Features 7 ...
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... The 56F8035/56F8025 includes many peripherals that are especially useful for industrial control, motion control, home appliances, general-purpose inverters, smart sensors, fire and port 56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor ...
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... ADC to the PWM and the connections to the PWM from the TMR and GPIO. These signals can control the PWM outputs in a similar manner as the PWM generator. See the 56F802x and 56F803x Peripheral Reference Manual for Freescale Semiconductor Figures 1-1, 1-2, 1-3, 1-4, 1-5, 1-6, and 1-7. ...
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... Data Y0 Arithmetic X0 Logic Unit (ALU) MAC and ALU Multi-Bit Shifter 56F8035/56F8025 Data Sheet, Rev. 6 ALU1 ALU2 Program R3 Memory XAB1 XAB2 PAB Data / Program PDB RAM CDBW CDBR XDB2 A0 B0 IPBUS C0 Interface D0 Freescale Semiconductor ...
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... To/From IPBus Bridge OCCS (ROSC / PLL / OSC) GPIO A GPIO B GPIO C GPIO D Freescale Semiconductor Interrupt Controller Low-Voltage Interrupt POR & LVI System POR SIM COP Reset COP IPBus (Continues on Figure 1-3) Figure 1-2 Peripheral Subsystem 56F8035/56F8025 Data Sheet, Rev. 6 Architecture Block Diagram RESET (Muxed with GPIOA7) ...
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... Figure 1-3 56F8035/56F8025 I/O Pin-Out Muxing (Part 1/5) 12 SYNC 3 SYNC SYNC SYNC0, SYNC1 on Figure 1-7 LIMIT on Figure 1-6 ANA0 ANA0 on ANA2 (V ) REFHA ANA3 (V ) REFLA ANA1 ANB0 ANB0 on ANB2 (V ) REFHB ANB3 (V ) REFLB ANB1 56F8035/56F8025 Data Sheet, Rev. 6 DAC SYNC on Figure 1-5 Figure 1-5 GPIOC2 GPIOC3 GPIOC1 Figure 1-5 GPIOC6 GPIOC7 GPIOC5 Freescale Semiconductor ...
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... To/From IPBus Bridge QSCI0 QSPI0 IPBus Figure 1-4 56F8035/56F8025 I/O Pin-Out Muxing (Part 2/5) Freescale Semiconductor RXD0, TXD0 2 TA2, TA3 on Figure 1-7 MISO0, MOSI0 2 SCLK0, SS0 2 2 SCL, SDA 2 2 56F8035/56F8025 Data Sheet, Rev. 6 Architecture Block Diagram GPIOB6 - 7 GPIOB2 - 3 GPIOB0 - 1 13 ...
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... Figure 1-6, Figure 1-7 CMPAI2 ANA0 on Figure 1-3 TB2 on Figure 1-4 2 TA0o, TA1o on Figure 1-7 3 DAC SYNC on Figure 1-3 RELOAD on Figure 1-6 ANB0 on Figure 1-3 CMPBI2 CMPBO on Figure 1-6, Figure 1-7 CMPBI3 CMPBI1 TA3 on Figure 1-7 FAULT2 on Figure 1-6 56F8035/56F8025 Data Sheet, Rev. 6 GPIOA8 GPIOC0 GPIOA10 GPIOB10 GPIOB11 GPIOA11 GPIOC4 GPIOA9 Freescale Semiconductor ...
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... To/From IPBus Bridge PWM RELOAD PSRC0 - 1 TA1 on IPBus Figure 1-6 56F8035/56F8025 I/O Pin-Out Muxing (Part 4/5) Freescale Semiconductor TA0 on Figure 1-7 2 TA2 - 3 on Figure 1-7 4 PWM0 - 3 FAULT0 PWMA4 - 5 1 FAULT1 FAULT2 1 FAULT3 Figure 1-7 3 56F8035/56F8025 Data Sheet, Rev. 6 Architecture Block Diagram GPIOA6 GPIOA0 - 3 GPIOA4 - FAULT1 on Figure 1-5 ...
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... TA3 on TA3 on RELOAD on 56F8035/56F8025 Data Sheet, Rev. 6 Figure 1-6 (PWM) Figure 1-6 (GPIOA6) Figure 1-6 (GPIOB5) Figure 1-6 (CMPA) Figure 1-3 (ADC) Figure 1-6 (PWM) Figure 1-6 (GPIOA4) Figure 1-5 (GPIOA8) Figure 1-4 (GPIOB2) Figure 1-6 (CMPB) Figure 1-3 (ADC) Figure 1-6 (PWM) Figure 1-6 (GPIOA5) Figure 1-5 (GPIOA9) Figure 1-4 (GPIOB3) Figure 1-6 (PWM) Freescale Semiconductor ...
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... Product Documentation The documents listed in Table 1-2 56F8035/56F8025. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at: http://www.freescale.com Table 1-2 56F8035/56F8025 Chip Documentation Topic DSP56800E Detailed description of the 56800E family architecture, Reference Manual 16-bit Digital Signal Controller core processor, and the ...
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... JTAG/Enhanced On-Chip Emulation (EOnCE) 1. Pins may be shared with other peripherals; see 18 Table 2-2, each table row describes the signal or Functional Group , DDA ) Ports 1 1 Table 2-2. 56F8035/56F8025 Data Sheet, Rev. 6 Number of Pins Freescale Semiconductor ...
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... GPIOB2 GPIOB2, MISO0, TA2, PSRC0 24 GPIOA6 GPIOA6, FAULT0, TA0 25 GPIOA10 GPIOA10, CMPAI2 26 GPIOA8 GPIOA8, FAULT1, TA2, CMPAI1 27 GPIOA5 GPIOA5, PWM5, TA3, FAULT2 Freescale Semiconductor Table 2-2 56F8035/56F8025 Pins Peripherals: GPIO I2C QSCI QSPI ADC PWM B6 SDA RXD0 B1 SDA SS0 B7 SCL TXD0 B5 FAULT3 ...
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... QSPI ADC PWM B0 SCL SCLK0 A4 PWM4 FAULT1 A2 PWM2 A3 PWM3 PWM1 A0 PWM0 D0 B11 D3 D1 56F8035/56F8025 Data Sheet, Rev. 6 Quad Power & Comp JTAG Misc Timer Ground TA2 V CAP XTAL CLKIN EXTAL TD1 CMPBO TMS TDO Freescale Semiconductor ...
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... GPIOB5 (TA1, FAULT3, CLKIN) or PWM GPIOB6 (RXD0, SDA, CLKIN) or TMRA or QSPI GPIOB7 (TXD0, SCL) or GPIOB TDI (GPIOD0) TDO (GPIOD1) JTAG/ EOnCE TCK (GPIOD2) or GPIOD TMS (GPIOD3) Figure 2-1 56F8035/56F8025 Signals Identified by Functional Group Freescale Semiconductor DDA SSA 1 1 ...
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... Port A GPIO — This GPIO pin can be individually programmed as an input or open drain output pin. Note that RESET functionality is disabled in this mode and the chip can only be reset via POR, COP reset, or software reset. After reset, the default state is RESET. 56F8035/56F8025 Data Sheet, Rev. 6 Signal Description 10.2.1. Freescale Semiconductor ...
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... Output GPIOA3 33 Input/ Output (PWM3) Output Return to Table 2-2 Freescale Semiconductor State During Reset Input, Port A GPIO — This GPIO pin can be individually programmed as internal an input or output pin. pull-up enabled PWM0 — This is one of the six PWM output pins. After reset, the default state is GPIOA0. ...
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... Fault2 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. After reset, the default state is GPIOA5. The peripheral functionality is controlled via the SIM. See 56F8035/56F8025 Data Sheet, Rev. 6 Signal Description Section 6.3.16. Section 6.3.16. Freescale Semiconductor ...
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... Input (TA3) Input/ Output (CMPBI1) Input Return to Table 2-2 Freescale Semiconductor State During Reset Input, Port A GPIO — This GPIO pin can be individually programmed as internal an input or output pin. pull-up enabled Fault0 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. TA0 — ...
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... QSPI0 module that the current transfer received. Serial Data — This pin serves as the I After reset, the default state is GPIOB1. The peripheral functionality is controlled via the SIM. See 56F8035/56F8025 Data Sheet, Rev. 6 Signal Description Section 6.3.16. Section 6.3.16 serial clock. Section 6.3.16 serial data line. Section 6.3.16. Freescale Semiconductor ...
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... Output Input (PSRC1) 8 The TA3 signal is also brought out on the GPIOA5 and GPIOA9 pins. Return to Table 2-2 Freescale Semiconductor State During Reset Input, Port B GPIO — This GPIO pin can be individually programmed as internal an input or output pin. pull-up enabled QSPI0 Master In/Slave Out — This serial data pin is an input to a master device and an output from a slave device ...
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... Serial Clock — This pin serves as the I After reset, the default state is GPIOB7. The peripheral functionality is controlled via the SIM. See 56F8035/56F8025 Data Sheet, Rev. 6 Signal Description Section 6.3.16 serial data line. Section 6.3.16) and the CLKMODE bit 2 C serial clock. Section 6.3.16. Freescale Semiconductor ...
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... Analog (ANA2) Input (V ) Analog REFHA Input Return to Table 2-2 Freescale Semiconductor State During Reset Input, Port B GPIO — This GPIO pin can be individually programmed as internal an input or output pin. pull-up enabled Comparator A Output— This is the output of comparator A. After reset, the default state is GPIOB10. The peripheral functionality is controlled via the SIM ...
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... Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB2 — Analog input to ADC B, Channel 2. V — Analog reference voltage high (ADC B). REFHB After reset, the default state is GPIOC6. 56F8035/56F8025 Data Sheet, Rev. 6 Signal Description Freescale Semiconductor ...
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... Input TDI 41 Input (GPIOD0) Input/ Output Return to Table 2-2 Freescale Semiconductor State During Reset Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB3 — Analog input to ADC B, Channel 3. V — Analog reference voltage low (ADC B). ...
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... TCK and has an on-chip pull-up resistor. enabled Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TMS. Note: Always tie the TMS pin to V 56F8035/56F8025 Data Sheet, Rev. 6 Signal Description through a 2.2K resistor. DD Freescale Semiconductor ...
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... The SIM is responsible for further dividing these frequencies by two, which will insure a 50% duty cycle in the system clock output. Freescale Semiconductor 56F8035/56F8025 Data Sheet, Rev. 6 Overview 33 ...
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... The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. 34 Figure 3-1 56F8035/56F8025 Data Sheet, Rev. 6 shows a typical crystal oscillator Freescale Semiconductor ...
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... Figure 3-2 External Ceramic Resonator Circuit 3.7 External Clock Input - Crystal Oscillator Option The recommended method of connecting an external clock is illustrated in source is connected to XTAL and the EXTAL pin is grounded. The external clock input must be generated using a relatively low impedance driver. Freescale Semiconductor Sample External Crystal Parameters 750 K ...
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... On-chip memory sizes for the device are summarized in identified in the “Use Restrictions” column of 36 56F8035/56F8025 CLKMODE = 1 XTAL EXTAL External GND or Clock GPIO 56F8035/56F8025 GPIO External Clock Table Table 4-1. 56F8035/56F8025 Data Sheet, Rev. 6 Figure 3-3. The external clock 4-1. Flash memories’ restrictions are Freescale Semiconductor ...
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... LVI 15 1-3 PLL 16 1-3 Freescale Semiconductor 56F8035 56F8025 32K x 16 16K x 16 Erase/Program via Flash interface unit and or 64KB or 32KB word writes to CDBW Usable by both the Program and Data or 8KB or 4KB Vector Base Address + P:$00 ...
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... Timer A, Channel 2 P:$60 Timer A, Channel 3 Reserved P:$6A Comparator A P:$6C Comparator B P:$6E Interval Timer 0 P:$70 Interval Timer 1 P:$72 Interval Timer 2 P:$74 ADC A Conversion Complete P:$76 ADC B Conversion Complete P:$78 ADC Zero Crossing or Limit Error P:$7A Reload PWM P:$7C PWM Fault P:$7E SW Interrupt Low Priority 56F8035/56F8025 Data Sheet, Rev (Continued) Interrupt Function Freescale Semiconductor ...
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... All addresses are 16-bit Word addresses. 2. This RAM is shared with Data space starting at address X: $00 0000; see 4.4 Data Map Table 4-5 Data Memory Map Begin/End Address X:$FF FFFF X:$FF FF00 X:$FF FEFF X:$01 0000 Freescale Semiconductor Table 4-3 and Table 4- Reset for 56F8035 Memory Allocation RESERVED ...
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... On-Chip Peripherals 4096 locations allocated RESERVED RESERVED RESERVED On-Chip Data RAM 2 8KB 1 for 56F8025 Memory Allocation EOnCE 256 locations allocated RESERVED On-Chip Peripherals 4096 locations allocated RESERVED RESERVED RESERVED 2 On-Chip Data RAM 4KB 56F8035/56F8025 Data Sheet, Rev. 6 Figure 4-1. Figure 4-2. Freescale Semiconductor ...
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... X:$FF FFFF OTX1 / ORX1 X:$FF FFFE OTX / ORX (32 bits) X:$FF FFFD OTXRXSR X:$FF FFFC OCLSR Freescale Semiconductor Dual Port RAM Dual Port RAM Table 4-7 EOnCE Memory Map Transmit Register Upper Word Receive Register Upper Word Transmit Register Receive Register Transmit and Receive Status and Control Register Core Lock / Unlock Status Register 56F8035/56F8025 Data Sheet, Rev ...
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... Breakpoint Unit Address Register 2 Breakpoint Unit Address Register 2 Breakpoint Unit Mask Register 2 Breakpoint Unit Mask Register 2 Reserved EOnCE Breakpoint Unit Counter Reserved Reserved Reserved External Signal Control Register Reserved Prefix Base Address TMRA X:$00 F000 56F8035/56F8025 Data Sheet, Rev. 6 Register Name Table Number 4-9 Freescale Semiconductor ...
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... Table 4-9 Quad Timer A Registers Address Map Register Acronym TMRA0_COMP1 TMRA0_COMP2 TMRA0_CAPT TMRA0_LOAD TMRA0_HOLD TMRA0_CNTR TMRA0_CTRL TMRA0_SCTRL TMRA0_CMPLD1 TMRA0_CMPLD2 TMRA0_CSCTRL TMRA0_FILT Freescale Semiconductor Prefix Base Address ADC X:$00 F080 PWM X:$00 F0C0 ITCN X:$00 F0E0 SIM X:$00 F100 COP X:$00 F120 OCCS X:$00 F130 PS X:$00 F140 GPIOA ...
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... Comparator Status and Control Register $2B Input Filter Register Reserved $30 Compare Register 1 $31 Compare Register 2 $32 Capture Register $33 Load Register $34 Hold Register $35 Counter Register $36 Control Register $37 Status and Control Register $38 Comparator Load Register 1 $39 Comparator Load Register 2 56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor ...
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... ADC_RSLT2 ADC_RSLT3 ADC_RSLT4 ADC_RSLT5 ADC_RSLT6 ADC_RSLT7 ADC_RSLT8 ADC_RSLT9 ADC_RSLT10 ADC_RSLT11 ADC_RSLT12 ADC_RSLT13 ADC_RSLT14 ADC_RSLT15 ADC_LOLIM0 Freescale Semiconductor (TMRA_BASE = $00 F000) Address Offset Register Description $3A Comparator Status and Control Register $3B Input Filter Register Reserved (ADC_BASE = $00 F080) Address Offset Register Description $0 Control Register 1 $1 Control Register 2 ...
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... Offset Register 7 $34 Power Control Register $35 Calibration Register Reserved (PWM_BASE = $00 F0C0) Address Offset Register Description $0 Control Register $1 Fault Control Register $2 Fault Status Acknowledge Register $3 Output Control Register $4 Counter Register $5 Counter Modulo Register $6 Value Register 0 56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor ...
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... Register Acronym ITCN_IPR0 ITCN_IPR1 ITCN_IPR2 ITCN_IPR3 ITCN_IPR4 ITCN_IPR5 ITCN_IPR6 ITCN_VBA ITCN_FIM0 ITCN_FIVAL0 ITCN_FIVAH0 ITCN_FIM1 ITCN_FIVAL1 ITCN_FIVAH1 Freescale Semiconductor (PWM_BASE = $00 F0C0) Address Offset Register Description $7 Value Register 1 $8 Value Register 2 $9 Value Register 3 $A Value Register 4 $B Value Register 5 $C Dead Time Register 0 ...
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... GPIO Peripheral Select Register 0 for GPIOB $16 GPIO Peripheral Select Register 1 for GPIOB $17 GPIO Peripheral Select Register for GPIOC and GPIOD $18 Internal Peripheral Source Select Register 0 for PWM $19 Internal Peripheral Source Select Register 1 for DACs 56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor ...
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... Table 4-15 Clock Generation Module Registers Address Map Register Acronym OCCS_CTRL OCCS_DIVBY OCCS_STAT OCCS_OCTRL OCCS_CLKCHK OCCS_PROT Table 4-16 Power Supervisor Registers Address Map Register Acronym PS_CTRL PS_STAT Freescale Semiconductor (SIM_BASE = $00 F100) Register Description $1A Internal Peripheral Source Select Register 2 for TMRA Reserved (COP_BASE = $00 F120) Address Offset Register Description $0 Control Register $1 ...
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... Interrupt Enable Register $6 Interrupt Edge Polarity Register $7 Interrupt Pending Register $8 Interrupt Edge-Sensitive Register $9 Push-Pull Output Mode Control Register $A Raw Data Input Register $B Output Drive Strength Control Register (GPIOC_BASE = $00 F170) Address Offset Register Description $0 Pull-up Enable Register 56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor ...
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... Table 4-19 GPIOC Registers Address Map Register Acronym GPIOC_DATA GPIOC_DDIR GPIOC_PEREN GPIOC_IASSRT GPIOC_IEN GPIOC_IEPOL GPIOC_IPEND GPIOC_IEDGE GPIOC_PPOUTM GPIOC_RDATA GPIOC_DRIVE Freescale Semiconductor (GPIOC_BASE = $00 F170) Address Offset Register Description $1 Data Register $2 Data Direction Register $3 Peripheral Enable Register $4 Interrupt Assert Register $5 Interrupt Enable Register $6 Interrupt Edge Polarity Register ...
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... Output Drive Strength Control Register (PIT0_BASE = $00 F190) Address Offset Register Description $0 Control Register $1 Modulo Register $2 Counter Register (PIT1_BASE = $00 F1A0) Address Offset Register Description $0 Control Register $1 Modulo Register $2 Counter Register (PIT2_BASE = $00 F1B0) Address Offset Register Description $0 Control Register 56F8035/56F8025 Data Sheet, Rev. 6 Register Description Freescale Semiconductor ...
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... DAC1_STEP DAC1_MINVAL DAC1_MAXVAL Table 4-26 Comparator A Registers Address Map Register Acronym CMPA_CTRL CMPA_STAT CMPA_FILT Table 4-27 Comparator B Registers Address Map Register Acronym CMPB_CTRL CMPB_STAT Freescale Semiconductor (PIT2_BASE = $00 F1B0) Address Offset Register Description $1 Modulo Register $2 Counter Register (DAC0_BASE = $00 F1C0) Address Offset Register Description $0 Control Register ...
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... Standard Speed Clock SCL High Count Register $C Standard Speed Clock SCL Low Count Register $E Fast Speed Clock SCL High Count Register $10 Fast Speed Clock SCL Low Count Register $16 Interrupt Status Register $18 Interrupt Mask Register 56F8035/56F8025 Data Sheet, Rev. 6 Register Description Freescale Semiconductor ...
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... I2C_RXFLR I2C_TXABRTSRC Table 4-31 Flash Module Registers Address Map Register Acronym FM_CLKDIV FM_CNFG FM_SECHI FM_SECLO FM_PROT FM_USTAT FM_CMD FM_DATA Freescale Semiconductor 2 C Registers Address Map (Continued) (I2C_BASE = $00 F280) Address Offset $1A Raw Interrupt Status Register $1C Receive FIFO Threshold Register $1E Transmit FIFO Threshold Register $20 ...
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... The 56800E core controls the masking of interrupt priority levels it will accept by setting the I0 56 (FM_BASE = $00 F400) (Continued) Address Offset $1B Information Option Register 1 $1C Reserved $1D Test Array Signature Register 4-2, Interrupt Vector Table Contents. 56F8035/56F8025 Data Sheet, Rev. 6 Register Description Freescale Semiconductor ...
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... I1 bits in its status register. Freescale Semiconductor 56F8035/56F8025 Data Sheet, Rev. 6 Functional Description 57 ...
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... Priorities Priority 3 Current Interrupt Required Nested Priority Level Exception Priority No interrupt or SWILP Priorities Priority 0 Priority 1 Priority 56F8035/56F8025 Data Sheet, Rev. 6 Exceptions Masked None Priority 0 Priorities 0, 1 Priorities Priorities Priorities 2, 3 Priority 3 Fast Interrupt Freescale Semiconductor ...
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... IRQ is enabled prior to entering the Wait or Stop mode. 5.6 Register Descriptions A register address is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level. Freescale Semiconductor any0 Level 0 64 -> 6 ...
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... Fast Interrupt Match 1 Register Fast Interrupt 1 Vector Address Low Register Fast Interrupt 1 Vector Address High Register IRQ Pending Register 0 IRQ Pending Register 1 IRQ Pending Register 2 IRQ Pending Register 3 Reserved Interrupt Control Register Reserved 56F8035/56F8025 Data Sheet, Rev. 6 Section Location 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 5.6.7 5.6.8 5.6.9 5.6.10 5.6.11 5.6.12 5.6.13 5.6.14 5.6.15 5.6.16 5.6.17 5.6.18 5.6.19 Freescale Semiconductor ...
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... FIVAH1 IRQP0 IRQP1 W R $10 IRQP2 W R $11 IRQP3 W Reserved R INT IPIC $16 ICTRL W Reserved = Reserved Figure 5-2 ITCN Register Map Summary Freescale Semiconductor LVI IPL RX_REG IPL QSPI0_XMIT IPL TMRA_2 IPL ...
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... IRQ is priority level 1 • IRQ is priority level 2 • IRQ is priority level LVI IPL RX_REG IPL TX_REG IPL 56F8035/56F8025 Data Sheet, Rev TRBUF IPL BKPT_U IPL STPCNT IPL Freescale Semiconductor 0 0 ...
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... This field is used to set the interrupt priority level for the EOnCE Step Counter IRQ. This IRQ is limited to priorities 1 through disabled by default. • IRQ disabled (default) • IRQ is priority level 1 • IRQ is priority level 2 • IRQ is priority level 3 Freescale Semiconductor 56F8035/56F8025 Data Sheet, Rev. 6 Register Descriptions 63 ...
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... IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 56F8035/56F8025 Data Sheet, Rev FM_CBE IPL FM_CC IPL FM_ERR IPL Freescale Semiconductor 0 0 ...
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... This field is used to set the interrupt priority level for the QSPI0 Transmitter Empty IRQ. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor ...
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... Base + $ Read 0 I2C_ERR IPL Write RESET Figure 5-6 Interrupt Priority Register 3 (IPR3 56F8035/56F8025 Data Sheet, Rev QSCI0_RCV QSCI0_RERR QSCI0_TIDL IPL IPL IPL Freescale Semiconductor 0 0 ...
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... This field is used to set the interrupt priority level for the QSCI0 Transmitter Idle IRQ. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor 2 C Error IRQ. This IRQ is limited to priorities 56F8035/56F8025 Data Sheet, Rev. 6 Register Descriptions 67 ...
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... IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level TMRA_1 IPL TMRA_0 IPL I2C_STAT IPL 56F8035/56F8025 Data Sheet, Rev I2C_TX IPL I2C_RX IPL I2C_GEN IPL Freescale Semiconductor ...
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... This field is used to set the interrupt priority level for the I priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 Freescale Semiconductor 2 C Status IRQ. This IRQ is limited to priorities 2 C Transmit IRQ. This IRQ is limited Receiver IRQ. This IRQ is limited General Call IRQ ...
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... IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level COMPB IPL COMPA IPL 56F8035/56F8025 Data Sheet, Rev Freescale Semiconductor ...
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... This field is used to set the interrupt priority level for the Reload PWM Interrupt IRQ. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor PWM_F IPL PWM_RL IPL ...
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... This field is used to set the interrupt priority level for the Programmable Interval Timer 2 IRQ. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 72 56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor ...
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... Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest-priority level 2 interrupt regardless of its location in the interrupt table prior to being declared as Fast Interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to the vector table. Freescale Semiconductor ...
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... Data Sheet, Rev FAST INTERRUPT 0 VECTOR ADDRESS HIGH FAST INTERRUPT Freescale Semiconductor ...
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... Fast Interrupt 1 defined in the FIM1 register. 5.6.15 IRQ Pending Register 0 (IRQP0) Base + $ Read Write RESET Figure 5-17 IRQ Pending Register 0 (IRQP0) Freescale Semiconductor FAST INTERRUPT 1 VECTOR ADDRESS LOW ...
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... No IRQ pending for this vector number PENDING[32:17 PENDING[48:33 56F8035/56F8025 Data Sheet, Rev Freescale Semiconductor ...
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... Nested interrupts may cause this field to be updated before the original interrupt service routine can read it. • Required nested exception priority levels are • Required nested exception priority levels are • Required nested exception priority levels are • Required nested exception priority level is 3 Freescale Semiconductor PENDING[63:49 ...
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... Core Reset 78 Current Interrupt Priority Level No interrupt or SWILP Priority 0 Priority 1 Priority Table 5-5 Reset Summary Priority Source RST 56F8035/56F8025 Data Sheet, Rev. 6 Required Nested Exception Priority Priorities Priorities Priorities 2, 3 Priority 3 Characteristics Core reset from the SIM Freescale Semiconductor ...
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... The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features. The System Integration Module’s functions are discussed in more detail in the following sections. Freescale Semiconductor Figure 5-22. ...
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... Peripheral protection control to provide runaway code protection for safety-critical applications • Controls output of internal clock sources to CLKO pin • Four general-purpose software control registers are reset only at power-on • Peripherals Stop mode clocking control 80 56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 81
... GPSB0 $15 GPSB1 $16 GPSCD $17 IPS0 $18 IPS1 $19 IPS2 $1A Freescale Semiconductor Register Name Control Register Reset Status Register Software Control Register 0 Software Control Register 1 Software Control Register 2 Software Control Register 3 Most Significant Half of JTAG ID Least Significant Half of JTAG ID Power Control Register Reserved CLKO Select Register ...
Page 82
... GPS_ GPS_ GPS_A9 GPS_A8 A11 A10 0 0 GPS_ GPS_B3 GPS_B2 GPS_ B10 IPS0_PSRC1 IPS0_PSRC0 0 0 IPS1_DSYNC1 IPS1_DSYNC0 IPS2_ TA1 Freescale Semiconductor 0 WAIT_ PWM TA0 PWM_ SD TA0_ SD GIPSP 0 GPS_ B0 GPS_ ...
Page 83
... Wait mode will be entered when the 56800E core executes a WAIT instruction and the WAIT_DISABLE field is write-protected until the next reset • The 56800E WAIT instruction will not cause entry into Wait mode and the WAIT_DISABLE field is write-protected until the next reset Freescale Semiconductor = 1 Read ...
Page 84
... When set, this bit indicates that the previous system reset was caused by an external reset. 6.3.2.6 Power-On Reset (POR)—Bit 2 This bit is set during a Power-On Reset 56F8035/56F8025 Data Sheet, Rev COP_ COP_ SWR EXTR POR 0 TOR LOR Freescale Semiconductor ...
Page 85
... This read-only register displays the least significant half of the JTAG ID for the chip. This register reads $801D. Base + $ Read Write RESET Figure 6-6 Least Significant Half of JTAG ID (SIM_LSHID) Freescale Semiconductor Software Control Data ...
Page 86
... PWM3 PWM2 PWM1 PWM0 56F8035/56F8025 Data Sheet, Rev LRSTDBY Freescale Semiconductor ...
Page 87
... Base + $ Read 0 TMRA_ PWM_ CR CR Write RESET Figure 6-9 Peripheral Clock Rate Register (SIM_PCR) 6.3.8.1 Reserved—Bits 15 This bit field is reserved. Each bit must be set to 0. Freescale Semiconductor I2C_ 56F8035/56F8025 Data Sheet, Rev ...
Page 88
... The clock is not provided to the Comparator A module (the Comparator A module is disabled) • The clock is enabled to the Comparator A module run clock DAC0 ADC 56F8035/56F8025 Data Sheet, Rev I2C QSCI0 QSPI0 Freescale Semiconductor 0 PWM 0 ...
Page 89
... The clock is enabled to the QSPI0 module 6.3.9.13 Reserved—Bit 1 This bit field is reserved. It must be set to 0. 6.3.9.14 PWM Clock Enable (PWM)—Bit 0 • The clock is not provided to the PWM module (the PWM module is disabled) Freescale Semiconductor module (the I C module is disabled module 56F8035/56F8025 Data Sheet, Rev. 6 ...
Page 90
... The clock is not provided to the Timer A1 module (the Timer A1 module is disabled) • The clock is enabled to the Timer A1 module PIT0 56F8035/56F8025 Data Sheet, Rev TA3 TA2 TA1 Freescale Semiconductor 0 TA0 0 ...
Page 91
... The clock is disabled during Stop mode • The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 6.3.11.4 Digital-to-Analog Converter 0 Clock Stop Disable (DAC0_SD)—Bit 12 • The clock is disabled during Stop mode Freescale Semiconductor ...
Page 92
... This bit field is reserved. It must be set to 0. 6.3.11.14 PWM Clock Stop Disable (PWM_SD)—Bit 0 • The clock is disabled during Stop mode • The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 92 56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 93
... The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register 6.3.12.7 Quad Timer A, Channel 2 Clock Stop Disable (TA2_SD)—Bit 2 • The clock is disabled during Stop mode • The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register Freescale Semiconductor ...
Page 94
... Note: The pipeline delay between setting this register set and using short I/O addressing with the new value is five instruction cycles. 94 “ Hard Coded” Address Portion 6 Bits from I/O Short Address Mode Instruction 56F8035/56F8025 Data Sheet, Rev. 6 Figure 6-14. Instruction Portion Freescale Semiconductor ...
Page 95
... Protection controls in this register have two bit values which determine the setting of the control and whether the value is locked. While a protection control remains unlocked, protection can be disabled and re-enabled by software. Once a protection control is locked, its value can only be altered by a chip reset, which restores its default non-locked value. Freescale Semiconductor ...
Page 96
... I/O pin when an I/O has two peripheral functions. Similar muxing is required on peripheral function inputs to receive input from the properly selected I/O pin 56F8035/56F8025 Data Sheet, Rev PCEP GIPSP Figure 6-18 illustrates the output path to Freescale Semiconductor 0 0 ...
Page 97
... This field selects the alternate function for GPIOA6. • FAULT0 - PWM FAULT0 Input (default) • TA0 - Timer A0 6.3.16.3 Configure GPIOA5 (GPS_A5)—Bits 11–10 This field selects the alternate function for GPIOA5. • PWM5 - PWM5 (default) Freescale Semiconductor GPIOA6 0 1 Table 2- ...
Page 98
... Configure GPIOA9 (GPS_A9)—Bits 3–2 This field selects the alternate function for GPIOA9 56F8035/56F8025 Data Sheet, Rev GPS_ GPS_ GPS_A9 GPS_A8 A11 A10 Freescale Semiconductor 0 0 ...
Page 99
... This field selects the alternate function for GPIOB5. • TA1 - Timer A1 (default) • FAULT3 - PWM FAULT3 Input • CLKIN - External Clock Input • Reserved 6.3.18.4 Reserved—Bits 10–8 This bit field is reserved. Each bit must be set to 0. Freescale Semiconductor GPS_B5 GPS_B3 ...
Page 100
... Write RESET Figure 6-22 GPIO Peripheral Select Register 1 for GPIOB (SIM_GPSB1) 100 GPS_ B11 56F8035/56F8025 Data Sheet, Rev GPS_ B10 Freescale Semiconductor 0 GPS_ B7 0 ...
Page 101
... Figure 6-23 GPIO Peripheral Select Register for GPIOC and GPIOD (SIM_GPSCD) 6.3.20.1 Reserved—Bits 15–13 This bit field is reserved. Each bit must be set to 0. 6.3.20.2 Configure GPIOD5 (GPS_D5)—Bit 12 This field selects the alternate function for GPIOD5. Freescale Semiconductor ...
Page 102
... IPSn settings should not be altered while an affected peripheral enabled (operational) configuration. See the 56F802x and 56F803x Peripheral Reference Manual for details. 102 SIM_GPSA0 Register PWM5 00 01 Timer A3 10 Comparator A Output (Internal) 56F8035/56F8025 Data Sheet, Rev. 6 GPIOA5_PEREN Register GPIOA5 0 GPIOA5 pin 1 Freescale Semiconductor ...
Page 103
... If the ADC conversion result in SAMPLE2 is less than the value programmed into the Low Limit register LLMT2, then PWM4 is set to 1 and PWM5 is set to 0 • 011 = CMPAO (Internal) - Use Comparator A output as PWM source • 100 = CMPBO (Internal) - Use Comparator B output as PWM source Freescale Semiconductor ...
Page 104
... CMPBO (Internal) - Use Comparator B output as PWM source • 11x = Reserved • 1x1 = Reserved 6.3.22 Internal Peripheral Source Select Register 1 for Digital-to-Analog Converters (SIM_IPS1) See Section 6.3.21 for general information about Internal Peripheral Source Select registers. 104 56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 105
... TA0 (Internal) - Use Timer A0 output as DAC SYNC input • 101 = TA1 (Internal) - Use Timer A1 output as DAC SYNC input • 11x = Reserved 6.3.23 Internal Peripheral Source Select Register 2 for Quad Timer A (SIM_IPS2) See Section 6.3.21 for general information about Internal Peripheral Source Select registers. Freescale Semiconductor ...
Page 106
... It divides the 106 IPS2_ IPS2_ TA3 TA2 56F8035/56F8025 Data Sheet, Rev IPS2_ TA1 Freescale Semiconductor ...
Page 107
... PLL and selected. Refer to the 56F802x and 56F803x Peripheral Reference Manual for further details. The peripheral clock enable controls can be used to disable an individual peripheral clock when it is not used. Freescale Semiconductor 56F8035/56F8025 Data Sheet, Rev. 6 Clock Generation Overview 2 C modules ...
Page 108
... The user configures the OCCS and SIM to enter Standby mode as shown in the previous description, followed by powering down the oscillator (ROPD). The only possible recoveries from this mode are: 1. External Reset 2. Power-On Reset 56F8035/56F8025 Data Sheet, Rev Table 6-2 Description Table 6-2. Freescale Semiconductor ...
Page 109
... X Figure 6-28 provides a graphic illustration of the details in use the OSC_CLK as their time base, since other system clocks are inactive during this phase of reset. Freescale Semiconductor C. The COP timer runs at OSC_CLK / 1024. The maximum frequency of Figure 6-28. The two asynchronous sources are the Table 6-3 Primary System Resets ...
Page 110
... ADC standby and conversion clocks are generated by a direct interface between the ADC and the OCCS module. 110 EXTENDED_POR CLKGEN_RST COMBINED_RST Delay 32 OSC_CLK Clock pulse shaper Delay 32 sys clocks pulse shaper 6.7. 56F8035/56F8025 Data Sheet, Rev. 6 JTAG Memory Subsystem OCCS PERIP_RST Peripherals 56800E Delay 32 sys clocks pulse shaper CORE_RST Freescale Semiconductor ...
Page 111
... CORE_RST. Both PERIP_RST and CORE_RST should be released on the negative edge of SYS_CLK_D as shown. This phased releasing of system resets is necessary to give some peripherals (for example, the Flash interface unit) set-up time prior to the 56800E core becoming active. Freescale Semiconductor 56F8035/56F8025 Data Sheet, Rev. 6 Clocks ...
Page 112
... Peripheral Reference Manual for the details. When flash 112 for Combined reset extension Switch on falling OSC_CLK 96 MSTR_OSC cycles 32 SYS_CLK cycles delay Switch on falling SYS_CLK 56F8035/56F8025 Data Sheet, Rev. 6 Switch on falling SYS_CLK 32 SYS_CLK cycles delay Freescale Semiconductor ...
Page 113
... Flash Lockout Recovery without mass erase A user can un-secure a secured device by programming the word $0000 into program memory location $00 7FF7. After completing the programming, both the JTAG TAP controller and the device must be reset Freescale Semiconductor sequence via JTAG, 56F8035/56F8025 Data Sheet, Rev. 6 ...
Page 114
... The specific mapping of GPIO port pins is shown Tables 2-2 and 2-3. Table 8-1 GPIO Ports Configuration Peripheral Function PWM, Timer, QSPI, Comparator, Reset 2 QSPI PWM, Clock, Comparator, Timer ADC, Comparator, QSCI Clock, Oscillator, DAC, JTAG 56F8035/56F8025 Data Sheet, Rev. 6 Reset Function GPIO, RESET GPIO GPIO GPIO, JTAG Freescale Semiconductor ...
Page 115
... FAULT1 / TA2 / CMPAI1 GPIOA9 FAULT2 / TA3 / CMPBI1 GPIOA10 CMPAI2 GPIOA11 CMPBI2 GPIOB0 SCLK0 / SCL GPIOB1 SS0 / SDA GPIOB2 MISO0 / TA2 / PSRC0 Freescale Semiconductor LQFP Package Pin 40 Defaults Defaults Defaults Defaults SIM register SIM_GPS is used to select between PWM4, TA2, and FAULT1 ...
Page 116
... ANA3 and V . REFLA Defaults to C3 SIM register SIM_GPS is used to select between ANB0 and CMPBI3. Defaults to C4 Defaults to C5 SIM register SIM_GPS is used to select between ANB2 and V . REFHB Defaults to C6 SIM register SIM_GPS is used to select between ANB3 and V . REFLB Defaults to C7 Freescale Semiconductor ...
Page 117
... TCK GPIOD3 TMS GPIOD4 EXTAL GPIOD5 XTAL / CLKIN 8.3 Reset Values Tables 8-1 and 8-2 detail registers for the 56F8035/56F8025; Figures maps and reset values. Freescale Semiconductor LQFP Package Pin 41 Defaults to TDI 44 Defaults to TDO 19 Defaults to TCK 43 Defaults to TMS 38 Defaults SIM register SIM_GPSCD is used to select between XTAL and CLKIN ...
Page 118
... IEPOL[15: IPR[15: IES[15: OEN[15: RAW DATA[15: DRIVE[15: Freescale Semiconductor ...
Page 119
... GPIOB_IEDGE GPIOB_PPOUTM GPIOB_RDATA GPIOB_DRIVE Figure 8-2 GPIOB Register Map Summary Freescale Semiconductor PU[15: D[15: ...
Page 120
... IA[15: IEN[15: IEPOL[15: IPR[15: IES[15: OEN[15: RAW DATA[15: DRIVE[15: Freescale Semiconductor ...
Page 121
... R $7 GPIOD_IPEND GPIOD_IEDGE GPIOD_PPOUTM GPIOD_RDATA GPIOD_DRIVE Figure 8-4 GPIOD Register Map Summary Freescale Semiconductor ...
Page 122
... Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. 122 are stress ratings only, and functional operation at the maximum = 3.0–3.6V, CL < 50pF 32MHz OP CAUTION of any voltages 56F8035/56F8025 Data Sheet, Rev the package. DD higher than Freescale Semiconductor ...
Page 123
... Pin Group 1: GPIO, TDI, TDO, TMS, TCK Pin Group 2: RESET, GPIOA7 Pin Group 3: ADC and Comparator Analog Inputs Pin Group 4: XTAL, EXTAL 10.1.1 ElectroStatic Discharge (ESD) Model Table 10-2 56F8035/56F8025 ESD Protection Characteristic ESD for Human Body Model (HBM) Freescale Semiconductor ( 0V) SS SSA Symbol Notes V ...
Page 124
... Data Sheet, Rev. 6 Typ Max Unit — — V — — Value Unit Notes (LQFP) 41 °C °C °C °C °C °C °C/W 5 Freescale Semiconductor ...
Page 125
... Program/Erase Cycles 1. Total chip source or sink current cannot exceed 75mA Default Mode Pin Group 1: GPIO, TDI, TDO, TMS, TCK Pin Group 2: RESET, GPIOA7 Pin Group 3: ADC and Comparator Analog Inputs Pin Group 4: XTAL, EXTAL Freescale Semiconductor ( 0V, V REFL x SSA Symbol ...
Page 126
... +/- 2 5.5V 0 +/- +/- -30 -60 0 +/- 2.5 0 +/- +/- — Typically DDA 40mV 0 +/- 2.5 A 0.35 — — — pF Freescale Semiconductor Test = I OHmax = I OLmax = 2. DDA = V DDA = — — — — — ...
Page 127
... All Peripheral modules enabled. TMR and PWM using 1X Clock ADC/DAC/Comparator powered off STOP 4MHz Device Clock Relaxation Oscillator on PLL powered off Processor Core in STOP state All peripheral module and core clocks are off ADC/DAC/Comparator powered off Freescale Semiconductor 1.5 2.0 2.5 3.0 3.5 Volt /I vs. V (Typical; Pull-Up Disabled) ...
Page 128
... greater, capacitor for proper operation. Ceramic µ 56F8035/56F8025 Data Sheet, Rev. 6 Typical @ 3.3V, 25°C Maximum@ 3.6V, 25° DDA DD DD 540 650 A 440 550 A Typ Max Unit Min 2.58 2.7 — V — 2.15 — V — 50 — mV — 1.8 1.9 V Freescale Semiconductor I DDA ...
Page 129
... Data Valid state, when a signal level has reached V • Data Invalid state, when a signal level is in transition between V Data1 Valid Data1 Data Invalid State Data Active Freescale Semiconductor pin. The specifications for this regulator are shown in Table 10-8. Regulator Parameters Symbol Min I — ...
Page 130
... V )/ Figure 10-4 External Clock Timing 56F8035/56F8025 Data Sheet, Rev. 6 Typ Max — 40 — — — — 1 Typ Max — — — — 3 — — 3 90% 50% 10 fall rise Freescale Semiconductor Unit Unit MHz ...
Page 131
... The core system clock will operate at 1/6 of the PLL output frequency. 3. This is the time required after the PLL is enabled to ensure reliable operation. 4. This is measured on the CLKO signal (programmed as System clock) over 264 System clocks at 32MHz System clock frequency and using an 8MHz oscillator frequency. Freescale Semiconductor Table 10-11 PLL Timing Symbol 1 ...
Page 132
... Degrees C (Junction) 56F8035/56F8025 Data Sheet, Rev. 6 Typical Maximum Unit — 8.05 MHz 200 kHz 400 — ps .08 — — % +1.0 to -1.5 +3 +2.0 to -2.0 % 100 125 150 175 Freescale Semiconductor ...
Page 133
... Parameters listed are guaranteed by design. 3. During Power-On Reset possible to use the 56F8035/56F8025 internal reset stretching circuitry to extend this period to 2^21T. GPIO pin (Input) Figure 10-6 GPIO Interrupt Timing (Negative Edge-Sensitive) Freescale Semiconductor Reset, Stop, Wait, Mode Select, and Interrupt Timing Symbol Typical Min t 4T ...
Page 134
... — — — — 56F8035/56F8025 Data Sheet, Rev. 6 Max Unit See Figure 10-7, 10-8, — ns 10-9, 10-10 — ns 10-10 — ns — ns 10-10 — ns — ns 10-7, 10-8, — ns 10-9, 10-10 — ns 10-10 — ns — ns 10-7, 10-8, — ns 10-9, 10-10 — ns 10-7, 10-8, — ns 10-9, 10-10 — ns 10- 10-10 15.2 ns 10-7, 10-8, 4.5 ns 10-9, 10-10 20.4 ns 10-7, 10-8, — ns 10-9, 10-10 — ns 10-7, 10-8, 11.5 ns 10-9, 10-10 10.0 ns 10-7, 10-8, 9.7 ns 10-9, 10-10 9.0 ns Freescale Semiconductor ...
Page 135
... Parameters listed are guaranteed by design. SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) t MISO (Input) MOSI (Output) Figure 10-7 SPI Master Timing (CPHA = 0) Freescale Semiconductor SS is held High on master MSB in Bits 14– Master MSB out Bits 14–1 ...
Page 136
... Figure 10-8 SPI Master Timing (CPHA = 1) 136 SS is held High on master MSB in Bits 14– Master MSB out Bits 14– 56F8035/56F8025 Data Sheet, Rev LSB in t (ref Master LSB out t R Freescale Semiconductor ...
Page 137
... SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) Figure 10-9 SPI Slave Timing (CPHA = 0) Freescale Semiconductor ELD Slave MSB out Bits 14– MSB in Bits 14–1 56F8035/56F8025 Data Sheet, Rev. 6 ...
Page 138
... Bits 14–1 Table 10-15 Timer Timing Symbol Min INHL P 125 OUT P 50 OUTHL 56F8035/56F8025 Data Sheet, Rev ELG Slave LSB out LSB Max Unit See Figure — ns 10-11 — ns 10-11 — ns 10-11 — ns 10-11 Freescale Semiconductor ...
Page 139
... Timer Inputs Timer Outputs Freescale Semiconductor P INHL OUTHL OUT Figure 10-11 Timer Timing 56F8035/56F8025 Data Sheet, Rev. 6 Quad Timer Timing P INHL P OUTHL 139 ...
Page 140
... RXD PW Figure 10-12 RXD Pulse Width TXD PW Figure 10-13 TXD Pulse Width 56F8035/56F8025 Data Sheet, Rev Max Unit See Figure (f /16) Mbps — MAX 1.04/BR ns 10-12 1.04/BR ns 10- — Master node bit periods — Slave node bit periods Freescale Semiconductor — — — — ...
Page 141
... If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line 1000 + 250 = 1250ns (according to the Standard mode I rmax SU; DAT released total capacitance of the one bus line Freescale Semiconductor 2 Table 10- Timing Standard Mode Minimum Maximum f 0 100 SCL 4 ...
Page 142
... LOW SCL t HD; STA S t HD; DAT Figure 10-14 Timing Definition for Fast and Standard Mode Devices on the I 142 SU; DAT t SU; STA SR t HIGH 56F8035/56F8025 Data Sheet, Rev BUF HD; STA SP t SU; STO Bus Freescale Semiconductor S ...
Page 143
... – Figure 10-15 Test Clock Input Timing Diagram TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output ) Figure 10-16 Test Access Port Timing Diagram Freescale Semiconductor Table 10-18 JTAG Timing Symbol Min Max f DC SYS_CLK — ...
Page 144
... GUARANTEED +/- 4 +/- 9 +/- 6 +/- 12 1.01 to .99 — V REFH — V DDA 0 +/- 2 0 — — 3 Figure 10-17 — Figure 10-17 — 10.0 Freescale Semiconductor Unit Bits MHz V 3 cycles 3 cycles 3 cycles 3 cycles 5 LSB 5 LSB mV mV — Ohms Bits ...
Page 145
... Equivalent resistance for the channel select mux; 100 ohms 4. Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only connected sampling time; 1.4pF Figure 10-17 Equivalent Circuit for A/D Loading Freescale Semiconductor 10- while the other charges to the analog input voltage. When REFLx ...
Page 146
... TBD TBD Min Typ Max 12 12 TBD — 2 TBD — 500.000 — — 11 — +/- 3 +/- 8.0 — +/- .8 < guaranteed — +/- 25 +/- 40 — +/- .5 +/- 1.5 V — V REFLX REFHX +.04V - .04V Freescale Semiconductor Unit mV ns Unit bits µS conv/sec µS 2 LSB 2 LSB — ...
Page 147
... Table 10-21 DAC Parameters (Continued) Parameter Conditions/Comments AC Specifications Signal-to-noise ratio Spurious free dynamic range Effective number of bits 1. No guaranteed specification within LSB = 0.806mV Freescale Semiconductor Symbol Min SNR SFDR ENOB or V DDA SSA 56F8035/56F8025 Data Sheet, Rev. 6 Digital-to-Analog Converter (DAC) Parameters ...
Page 148
... Summation is performed over all output pins with capacitive loads • TotalPower is expressed in mW 148 2 *F CMOS power dissipation corresponding to the Intercept 1.3 0.11mW / pF 1.15mW 0.11mW / pF Table 10-22 provides coefficients for calculating power dissipated 56F8035/56F8025 Data Sheet, Rev *F, although simulations on two Slope Freescale Semiconductor ...
Page 149
... Part 11 Packaging 11.1 56F8035/56F8025 Package and Pin-Out Information This section contains package and pin-out information for the 56F8035/56F8025. This device comes in a 44-pin Low-profile Quad Flat Pack (LQFP). the mechanical parameters and Freescale Semiconductor Figure 11-1 shows the package outline, Table 11-1 lists the pin-out. ...
Page 150
... MARK PIN 34 PIN 1 PIN 23 PIN 12 56F8035/56F8025 Data Sheet, Rev. 6 GPIOA3 / PWM3 GPIOA2 / PWM2 GPIOA4 / PWM4 / TA2 / FAULT1 GPIOB0 / SCLK0 / SCL GPIOA5 / PWM5 / TA3 / FAULTA2 GPIOA8 / FAULTA1 / TA2 / CMPAI1 GPIOA10 / CMPAI2 GPIOA6 / FAULT0 / TA0 GPIOB2 / MISO0 / TA2 / PSRC0 Freescale Semiconductor ...
Page 151
... GPIOC4 18 ANB0 &CMPBI3 8 GPIOC5 19 ANB1 9 GPIOC6 20 ANB2 / V REFHB 10 GPIOC7 21 ANB3 / V REFLB DDA 1. Alternate signals are in italic Freescale Semiconductor Pin Signal Name Signal Name # V 23 GPIOB2 SSA MISO0 / TA2 / PSRC0 GPIOC3 24 GPIOA6 ANA3 / V FAULT0 / TA0 REFLA GPIOC2 25 GPIOA10 ANA2 / V CMPAI2 REFHA ...
Page 152
... Figure 11-2 56F8035/56F8025 44-Pin LQFP Mechanical Information ( Please see www.freescale.com for the most current case outline. 152 56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 153
... Figure 11-3 56F8035/56F8025 44-Pin LQFP Mechanical Information ( Please see www.freescale.com for the most current case outline. Freescale Semiconductor 56F8035/56F8025 Package and Pin-Out Information 56F8035/56F8025 Data Sheet, Rev. 6 153 ...
Page 154
... Figure 11-4 56F8035/56F8025 44-Pin LQFP Mechanical Information ( Please see www.freescale.com for the most current case outline. 154 56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 155
... JT D where Thermocouple temperature on top of package ( T = Thermal characterization parameter ( Power dissipation in package (W) D Freescale Semiconductor , can be obtained from the equation C/W) . For instance, the user can change the size of the heat CA ) can be used to determine the junction temperature with a JT ...
Page 156
... CAUTION of any voltages (GND) pin SS /V Ceramic and tantalum capacitors tend to provide better DDA SSA. with approximately 100µF, plus the number of 0.1µF ceramic capacitors 56F8035/56F8025 Data Sheet, Rev. 6 higher than pin on the 56F8035/56F8025 and DD and V (GND Freescale Semiconductor ...
Page 157
... Electrical Design Considerations , and V pins SSA and V SS SSA and V traces. DDA SSA 2 C, the less than 0V. If positive in Ambient Temperature Order Number (MHz) Range 32 -40° 105° C MC56F8035VLD* 32 -40° 105° C MC56F8025VLD* 32 -40° 125° C MC56F8025MLD* are 157 ...
Page 158
... ADC_ADRSL T0-7 0xF08C ADC_ADRSLT8-15 0xF094 ADC_ADLLMT0-7 0XF09C 0XF0A3 ADC_ADHLMT0-7 0XF0A4 0XF0AB ADC_ADOFS0-7 0XF0AC 0XF0B3 ADC_ADPOWER ADC_ADCAL COPCTL COPCTL COPTO COPTO COPCTR COPCTR Freescale Semiconductor Memory Address End 0xF080 0xF081 0xF082 0xF083 0xF084 0xF085 0xF086 0xF087 0xF088 0xF089 0xF08A 0xF08B 0XF093 0XF09B 0XF0B4 ...
Page 159
... Interrupt Register Clear Receive Over CLRRXOVR Interrupt Register Clear Transmit Over CLRTXOVR Register Clear Read Required CLRRDREQ Interrupt Register Clear Transmit Abort CLRTXABRT Interrupt Register Freescale Semiconductor Data Sheet Legacy New Acronym Acronym 2 Inter-Integrated Circuit Interface (I IBCR I2C_CTRL I2C_TAR I2C_SAR I2C_DATA ...
Page 160
... PLLCR PLLCR PLLDB PLLDB PLLSR PLLSR OSCTL OSCTL PLLCLCHK OCCS_CLCHK PLLPROT OCCS_PROT FMCLKD FMCLKD FMCR FMCR FMSECH FMSECH FMSECL FMSECL Freescale Semiconductor Memory Address End 0xF2AC 0xF2AE 0xF2B0 0xF2B2 0xF2B4 0xF2B6 0xF2B8 0xF2BA 0xF2BC 0xF2C0 0xF2FA 0xF2FB 0xF2FC 0xF2FD 0xF2FE 0xF2FF ...
Page 161
... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® ...