MC56F8035VLD Freescale Semiconductor, MC56F8035VLD Datasheet - Page 106

• Manufacturer Part Number: MC56F8035VLD
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLD

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

6.3.23.1
This bit field is reserved. Each bit must be set to 0.
6.3.23.2
This field selects the alternate input source signal to feed Quad Timer A, input 3.
6.3.23.3
This bit field is reserved. Each bit must be set to 0.
6.3.23.4
This field selects the alternate input source signal to feed Quad Timer A, input 2.
6.3.23.5
This bit field is reserved. Each bit must be set to 0.
6.3.23.6
This field selects the alternate input source signal to feed Quad Timer A, input 1.
6.3.23.7
This bit field is reserved. Each bit must be set to 0.
For Timer A to detect the PWM SYNC signal, the clock rate of both the PWM module and Timer A
module must be identical, at either the system clock rate or 3X system clock rate.
6.4 Clock Generation Overview
The SIM uses the master clock (2X system clock) at a maximum of 64MHz from the OCCS module to
produce a system clock at a maximum of 32MHz for the peripheral, core, and memory. It divides the
106
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Base + $1A
RESET
Read
Write
0 = I/O pin (External) - Use Timer A3 input/output pin
1 = PWM SYNC (Internal) - Use PWM reload synchronization signal
0 = I/O pin (External) - Use Timer A2 input/output pin
1 = CMPBO (Internal) - Use Comparator B output
0 = I/O pin (External) - Use Timer A1 input/output pin
1 = CMPAO (Internal) - Use Comparator A output
Figure 6-27 Internal Peripheral Source Select Register for TMRA (SIM_IPS2)
Reserved—Bits 15–13
Select Input Source for TA3 (IPS2_TA3)—Bit 12
Reserved—Bits 11–9
Select Input Source for TA2 (IPS2_TA2)—Bit 8
Reserved—Bits 7–5
Select Input Source for TA1 (IPS2_TA1)—Bit 4
Reserved—Bits 3–0
15
0
0
14
0
0
13
0
0
IPS2_
TA3
12
0
56F8035/56F8025 Data Sheet, Rev. 6
11
0
0
10
0
0
9
0
0
IPS2_
TA2
8
0
7
0
0
6
0
0
5
0
0
IPS2_
TA1
4
0
3
0
0
Freescale Semiconductor
2
0
0
1
0
0
0
0
0