MC56F8035VLD Freescale Semiconductor, MC56F8035VLD Datasheet - Page 37

• Manufacturer Part Number: MC56F8035VLD
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLD

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

4.2 Interrupt Vector Table
Table 4-2
peripherals. The table is organized with higher-priority vectors at the top and lower-priority interrupts
lower in the table. As indicated, the priority of an interrupt can be assigned to different levels, allowing
some control over interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For
a selected priority level, the lowest vector number has the highest priority.
The location of the vector table is determined by the Vector Base Address (VBA). Please see
for the reset value of the VBA.
By default, the chip reset address and COP reset address will correspond to vector 0 and 1 of the interrupt
vector table. In these instances, the first two locations in the vector table must contain branch or JMP
instructions. All other entries must contain JSR instructions.
Freescale Semiconductor
core
core
core
core
core
core
core
core
core
core
core
core
core
core
LVI
PLL
Peripheral
provides the 56F8035/56F8025’s reset and interrupt priority structure, including on-chip
Program Flash (PFLASH)
Unified RAM (RAM)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Number
Vector
On-Chip Memory
3
3
3
3
1-3
1-3
1-3
1-3
1-3
2
1
0
1-3
1-3
Priority
Table 4-2 Interrupt Vector Table Contents
Level
Table 4-1 Chip Memory Configurations
P:$00
P:$02
P:$04
P:$06
P:$08
P:$0A
P:$0C
P:$0E
P:$10
P:$12
P:$14
P:$16
P:$18
P:$1A
P:$1E
P:$20
Vector Base
56F8035/56F8025 Data Sheet, Rev. 6
Address +
56F8035 56F8025
32K x 16
or 64KB
4K x 16
or 8KB
16K x 16
or 32KB
2K x 16
or 4KB
EOnCE Step Counter
EOnCE Breakpoint Unit
Low-Voltage Detector (Power Sense)
Phase-Locked Loop
Reserved for Reset Overlay
Reserved for COP Reset Overlay
Illegal Instruction
SW Interrupt 3
HW Stack Overflow
Misaligned Long Word Access
EOnCE Trace Buffer
EOnCE Transmit Register Empty
EOnCE Receive Register Full
SW Interrupt 2
SW Interrupt 1
SW Interrupt 0
Reserved
Erase/Program via Flash interface unit and
Usable by both the Program and Data
word writes to CDBW
Interrupt Function
Use Restrictions
memory spaces
2
1
Interrupt Vector Table
Section 5.6.8
37