LH540235M-20 SHARP [Sharp Electrionic Components], LH540235M-20 Datasheet - Page 6

• Manufacturer Part Number: LH540235M-20
• Description: 2048 x 18 / 4096 x 18 Synchronous FIFOs
• Manufacturer: SHARP [Sharp Electrionic Components]

LH540235/45
PIN DESCRIPTIONS
BOLD ITALIC = Enhanced Operating Mode
6
D
RS
EMODE
WCLK
WEN
RCLK
REN
OE
0
– D
PIN
17
Data Inputs
Reset
Enhanced
Operating
Mode
Write Clock
Write Enable
Read Clock
Read Enable
Output Enable
NAME
TYPE
PIN
I
I
I
I
I
I
I
I
1
Data inputs from an 18-bit bus.
When RS is taken LOW, the FIFO’s internal read and write pointers are set to
address the first physical location of the RAM array; FF, PAF, and HF go HIGH;
and PAE and EF go LOW. The programmable-flag-offset registers and the
Control Register are set to their default values. (But see the description of
EMODE , below.) A reset operation is required before an initial read or write
operation after power-up.
When EMODE is tied LOW, the default setting for Control Register bits 00-
05 after a reset operation changes to HIGH rather than LOW, thus enabling
all Control-Register-controllable Enhanced Operating Mode features, and
allowing access to the Control Register for reprogramming or readback
(see Tables 1, 2, and 5). If this behavior is desired, EMODE may be
grounded; however, Control Register bits 00-06 still may be individually
programmed to selectively enable or disable certain of the Enhanced Mode
features, even though those features associated with interlocked-paralleled
operation always are enabled whenever EMODE is being asserted (see
Table 2). Alternatively, EMODE may be tied to V
functionally IDT-compatible, and the Control Register is not accessible or
visible, and all of its bits remain LOW. Controlling EMODE dynamically
during system operation is not recommended.
Data is written into the FIFO on a LOW-to-HIGH transition of WCLK, whenever
WEN (Write Enable) is being asserted (LOW), and LD is HIGH. If LD is LOW, a
programmable register rather than the internal FIFO memory is written into. In
the Enhanced Operating Mode, whenever Control Register bit 06 is HIGH,
WEN
signal.
When WEN is LOW and LD is HIGH, an 18-bit data word is written into the FIFO
on every LOW-to-HIGH transition of WCLK. When WEN is HIGH, the FIFO
internal memory continues to hold the previous data (see Table 3). Data will not
be written into the FIFO if FF is LOW. In the Enhanced Operating Mode,
whenever Control Register bit 06 is HIGH, WEN
produce an effective internal write-enable signal.
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK whenever
REN (Read Enable) is being asserted (LOW), and LD is HIGH. If LD is LOW, a
programmable register rather than the internal FIFO memory is read from. In the
Enhanced Operating Mode, whenever Control Register bit 06 is HIGH, REN
is ANDed with REN (and whenever Control Register bit 05 is HIGH, also
with OE) to produce an effective internal read-enable signal.
When REN is LOW and LD is HIGH, an 18-bit data word is read from the FIFO
on every LOW-to-HIGH transition of RCLK. When REN is HIGH, and/or also
when EF is LOW, the FIFO’s output register continues to hold the previous data
word, whether or not Q
the Enhanced Operating Mode, whenever Control Register bit 06 is HIGH,
REN
also with OE) to produce an effective internal read-enable signal.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are
connected. If OE is HIGH, the FIFO’s outputs are in high-Z (high-impedance)
state. In the Enhanced Operating Mode, OE not only continues to control
the outputs in this same manner, but also can function as an additional
ANDing input to the combined effective read-enable signal, along with REN
and REN
2
2
is ANDed with REN (and whenever Control Register bit 05 is HIGH,
is ANDed with WEN to produce an effective internal write-enable
2
2
, whenever Control Register bit 05 is HIGH (see Table 5).
0
– Q
17
(the data outputs) are enabled (see Table 3). In
DESCRIPTION
2048 x 18/4096 x 18 Synchronous FIFOs
CC,
2
is ANDed with WEN to
2
so that the FIFO is
2
2
2
2