LH540235M-20 SHARP [Sharp Electrionic Components], LH540235M-20 Datasheet - Page 16

• Manufacturer Part Number: LH540235M-20
• Description: 2048 x 18 / 4096 x 18 Synchronous FIFOs
• Manufacturer: SHARP [Sharp Electrionic Components]

LH540235/45
available 18 bits. Figure 6 shows which bit positions of
each register are operational. The two Programmable-
Flag-Offset-Value Registers each contain an offset value
in bits 0-10 (LH540235) or bits 0-11 (LH540245); bits
11-17 (LH540235) or bits 12-17 (LH540245) are unused.
The default values for both offsets are 127
ure 6 and in Table 5. For the Control Register , in the
IDT-Compatible Operating Mode, with EMODE deas-
serted (HIGH), the default value for all Control-Register
bits is zero (LOW). In the Enhanced Operating Mode,
with EMODE asserted (LOW), the default value for
bits 00-05 is HIGH, and the default value for bits 06-11
is LOW.
BOLD ITALIC = Enhanced Operating Mode
16
None of these three registers makes use of all of its
The Control Register configuration is shown in Fig-
WORD 2
WORD 0
WORD 1
CONTROL-REGISTER BITS:
BOLD ITALIC = Enhanced Operating Mode.
NOTES:
3
1. Default offset values all are 127
2. Bits 11-17 (LH540235) or bits 12-17 (LH540245) of both offset-value registers should
3. This bit position is used for offset values in the LH540245 only. In the LH540235, it
4. See the Control-Register Format table for the default states of the Control Register,
5. The assertion of EMODE (LOW) forces Control Register bits 00-05 HIGH during a reset operation.
5
4
0
6
2
1
in all cases be programmed LOW (zero).
always should be programmed LOW.
for EMODE = HIGH (IDT-Compatible Operating Mode) and for EMODE = LOW (Enhanced Operating Mode).
The Control Register is not accessible or visible in IDT-Compatible Operating Mode.
After that, these bits may be programmed at will.
= Reserved. Do not load with non-zero information.
Future use to control depth cascading and interlocked paralleling.
Enables suppressing reading whenever data outputs are disabled.
Makes PAF synchronous.
Makes HF synchronous. (See the Control-Register Format
table for the encoding of bits 02-03.)
Makes PAE synchronous.
Selects reinitialized addressing of the programmable registers.
17
17
17
10
= 7F
16
12
Figure 5. Programmable Registers
12
12
.
10
.
11
11
11
3
3
Reserved for
future use.
10
10
PROGRAMMABLE-ALMOST-EMPTY-FLAG-OFFSET VALUE
PROGRAMMABLE-ALMOST-FULL-FLAG-OFFSET VALUE
asserted (are both LOW), the 18-bit data word from the
data inputs D
Almost-Empty-Flag-Offset-Value Register at the first ris-
ing edge (LOW-to-HIGH transition) of the write clock
(WCLK). (See Table 3.) If LD and WEN continue to be
simultaneously asserted, another 18-bit data word from
the data inputs D
ble-Almost-Full-Flag-Offset-Value Register at the second
rising edge of WCLK.
Whenever LD and WEN are simultaneously being
CONTROL REGISTER
7
See Table 5 for a
more complete
description of these
effects.
2048 x 18/4096 x 18 Synchronous FIFOs
6
6
0
– D
0
5
5
– D
17
is written into the Programmable-
4, 5
17
4
4
is written into the Programma-
3
3
2
2
1, 2
1
1
1, 2
540235-4
0
0
0
0