LH540235M-20 SHARP [Sharp Electrionic Components], LH540235M-20 Datasheet - Page 33
LH540235M-20
Manufacturer Part Number
LH540235M-20
Description
2048 x 18 / 4096 x 18 Synchronous FIFOs
Manufacturer
SHARP [Sharp Electrionic Components]
Datasheet
1.LH540235M-20.pdf
(46 pages)
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TIMING DIAGRAMS (cont’d)
2048 x 18/4096 x 18 Synchronous FIFOs
Enhanced Operating Mode Timing Diagram
NOTE:
1. t
2. The internal state of the FIFO:
rising RCLK edge for HF to change predictably during the current
clock cycle. If the time between the rising edge of WCLK and the
rising edge of RCLK is less than t
that HF will change state until the next following RCLK edge.
SKEW2
At
At
At
Q
D
WCLK
0
0
RCLK
A
C
B
WEN
- D
- Q
REN
is the minimum time between a rising WCLK edge and a
OE
HF
, half+1 words.
, exactly half full.
, half+1 words again.
17
17
LOW
t
ENS
A
t
DS
DATA WRITE 1
t
ENH
DATA IN OUTPUT REGISTER
t
SKEW2
Figure 20. Half-Full-Flag Timing, When Synchronized
SKEW2
(1)
to Output Port (Enhanced Operating Mode)
, then it is not guaranteed
t
ENS
B
t
t
ENH
HFS
t
A
t
ENS
C
t
DS
DATA WRITE 2
t
HFS
t
ENH
t
SKEW2
DATA READ
(1)
t
HFS
LH540235/45
540235-26
33
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